Kramadhati V Ravi from 4379 Barton Rd, Loomis, CA 95650, age 84, Phone: 4153277175

Low Cte Substrate For Reflective Euv Lithography
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US Patent:

6387572, May 14, 2002
Filed:

Sep 13, 1999
Appl. No.:

09/395310
Inventors:

Tom X. Tong - Milpitas CA
Kramadhati V. Ravi - Atherton CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G03F 900
US Classification:

430 5, 378 35
Abstract:

A substrate for reflective EUV lithography that includes a first layer that has a low coefficient of thermal expansion and a second layer, formed on the first layer, that has a high surface quality. The second layer may have a coefficient of thermal expansion that is higher than the coefficient of thermal expansion of the first layer.

Method For The Manufacture Of Semiconductor Devices And Circuits
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US Patent:

6406981, Jun 18, 2002
Filed:

Jun 30, 2000
Appl. No.:

09/607252
Inventors:

Kramadhati V. Ravi - Atherton CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 2120
US Classification:

438489, 117 89, 117 90, 117 95, 117106, 438488
Abstract:

A method of coupling a single crystal semiconductor layer on a surface of a substrate comprising a polycrystalline semiconductor material such that the single crystal layer and the polycrystalline material are in direct contact.

Silicon Wafers For Cmos And Other Integrated Circuits
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US Patent:

6423615, Jul 23, 2002
Filed:

Sep 22, 1999
Appl. No.:

09/401555
Inventors:

Kramadhati V. Ravi - Atherton CA
Li Ling - Fremont CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 2146
US Classification:

438458, 438231, 148DIG 41
Abstract:

Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the water and forming at least one electrical circuit element in the near-surface region.

Amorphous Carbon Insulation And Carbon Nanotube Wires
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US Patent:

6548313, Apr 15, 2003
Filed:

May 31, 2002
Appl. No.:

10/159236
Inventors:

Kramadhati V. Ravi - Atherton CA
Eric C. Hannah - Pebble Beach CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 2100
US Classification:

438 6, 438128, 438479, 438430
Abstract:

An apparatus includes a carbon nanotube coupled with a first device and a second device of an integrated circuit, wherein electrons can flow between the first device and the second device along the carbon nanotube. Doped amorphous carbon is deposited on the integrated circuit structure. The doped amorphous carbon is planarizing and patterned to form a trench. Carbon based precursor material is deposited in the trench. The carbon based precursor material is converted into the carbon nanotube, wherein the carbon nanotube connects the first device with the second device.

Reliable Opposing Contact Structure
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US Patent:

6621022, Sep 16, 2003
Filed:

Aug 29, 2002
Appl. No.:

10/231565
Inventors:

Qing Ma - San Jose CA
Kramadhati V. Ravi - Atherton CA
Valluri Rao - Saratoga CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01H 102
US Classification:

200267, 200181
Abstract:

A switch structure having multiple contact surfaces that may contact each other. One or more of the contact surfaces may be coated with a resilient material such as diamond.

Silicon Wafers For Cmos And Other Integrated Circuits
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US Patent:

6667522, Dec 23, 2003
Filed:

May 23, 2002
Appl. No.:

10/155632
Inventors:

Kramadhati V. Ravi - Atherton CA
Li Ling - Fremont CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 2936
US Classification:

257372
Abstract:

Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Integrated circuits or other devices may include a semiconductor wafer with a substantially uniformly boron-doped bulk region and a reduced boron concentration layer near a surface of the wafer. An electrical circuit element may be provided in the reduced boron concentration layer.

Techniques To Fabricate A Reliable Opposing Contact Structure
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US Patent:

6706981, Mar 16, 2004
Filed:

Mar 13, 2003
Appl. No.:

10/389725
Inventors:

Qing Ma - San Jose CA
Kramadhati V. Ravi - Atherton CA
Valluri Rao - Saratoga CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01H 5700
US Classification:

200181, 200267
Abstract:

A switch structure having multiple contact surfaces that may contact each other. One or more of the contact surfaces may be coated with a resilient material such as diamond.

Amorphous Carbon Insulation And Carbon Nanotube Wires
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US Patent:

6730972, May 4, 2004
Filed:

Jan 28, 2003
Appl. No.:

10/352639
Inventors:

Kramadhati V. Ravi - Atherton CA
Eric C. Hannah - Pebble Beach CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 2976
US Classification:

257379, 257 52, 257382, 257401
Abstract:

An apparatus includes a carbon nanotube coupled with a first device and a second device of an integrated circuit, wherein electrons can flow between the first device and the second device along the carbon nanotube. Doped amorphous carbon is deposited on the integrated circuit structure. The doped amorphous carbon is planarizing and patterned to form a trench. Carbon based precursor material is deposited in the trench. The carbon based precursor material is converted into the carbon nanotube, wherein the carbon nanotube connects the first device with the second device.

Kramadhati V Ravi