Kiran S Puranik

US Patent:

8122177, Feb 21, 2012

Filed:

May 19, 2009

Appl. No.:

12/468340

Inventors:

Kiran S. Puranik - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 13/28

US Classification:

710308, 710316

Abstract:

An integrated circuit (“IC”) includes a peripheral component interconnect express (“PCIe”) root complex having a central processing unit (“CPU”), a memory controller configured to control a main memory of a PCIe system, and a PCIe port coupled to a PCIe endpoint device through a PCIe switch. The PCIe endpoint device is configured to initiate data transfer between the main memory and the PCIe endpoint device.

US Patent:

8352648, Jan 8, 2013

Filed:

Nov 22, 2010

Appl. No.:

12/952139

Inventors:

Kiran S. Puranik - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 3/00
G06F 5/00

US Classification:

710 36, 710 53

Abstract:

An embodiment of a method for credit-based flow control is disclosed. For this embodiment of the method, a first transaction layer packet from a sending device is loaded into a receiver buffer of a receiving device. A second transaction layer packet is loaded into the receiver buffer, where the second transaction layer packet is of a different packet type than the first transaction layer packet. The first transaction layer packet is unloaded from the receiver buffer without return of a credit for the unloading of the first transaction layer packet from the receiver buffer. The first transaction layer packet is loaded into a side buffer, and the credit for the first transaction layer packet is sent to the sending device responsive to unloading or anticipated unloading of the first transaction layer packet from the side buffer.

US Patent:

7852757, Dec 14, 2010

Filed:

Mar 10, 2009

Appl. No.:

12/401032

Inventors:

Kiran S. Puranik - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 31/08

US Classification:

370229, 370419, 370412, 710 52

Abstract:

An integrated circuit (“IC”) with a peripheral component interconnect express (“PCIe”) has at least two data sinks () and a data source () capable of providing data packets to either data sink. A switch () of the PCIe system includes a first buffer () queuing data packets for one of the data sinks and a second buffer () queuing data packets for the other data sink. A status detector () detects when the first buffer equals or exceeds a selected buffer threshold, and a status-based flow control transmitter () sends a data link layer packet (“DLLP”) to the status-based flow control receiver () of the data source to cease transmitting first data packets while continuing to transmit second data packets.

US Patent:

20200044895, Feb 6, 2020

Filed:

Aug 2, 2018

Appl. No.:

16/053384

Inventors:

- San Jose CA, US
Kiran S. Puranik - Fremont CA, US
Jaideep Dastidar - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04L 12/54
H04L 29/06

Abstract:

A method and a system for transparently overlaying a logical transport network over an existing physical transport network is disclosed. The system designates a virtual channel located in a first transaction layer of a network conforming to a first network protocol. The system assembles a transaction layer packet in a second logical transaction layer of a second network protocol that is also recognizable by the first transaction layer. The system transfers the transaction layer packet from the second transaction layer to the virtual channel. The system transmits the transaction layer packet over the first transaction layer using the designated virtual channel over the network.