Kent H Haselhorst

US Patent:

6505306, Jan 7, 2003

Filed:

Sep 15, 1999

Appl. No.:

09/396973

Inventors:

Herman Lee Blackmon - Rochester MN
Robert Allen Drehmel - Goodhue MN
Kent Harold Haselhorst - Byron MN
James Anthony Marcella - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 305

US Classification:

714 6, 714 42

Abstract:

An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.

US Patent:

6513091, Jan 28, 2003

Filed:

Nov 12, 1999

Appl. No.:

09/439586

Inventors:

Herman Lee Blackmon - Rochester MN
Robert Allen Drehmel - Goodhue MN
Kent Harold Haselhorst - Byron MN
James Anthony Marcella - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1314

US Classification:

710316, 370362

Abstract:

A method and apparatus for routing data between bus devices, where each bus device is connected to a centralized switch via a point-to-point bus connection. The plurality of point-to-point bus connections collectively form a system bus. After a command is issued on the system bus, each bus device responds to the issued command by transmitting an address status response to a response combining logic module. The response combining logic module identifies which of the bus devices responded with a positive acknowledgment to the issued command, then forwards a device identifier of the bus device responding with the positive acknowledgment to the switch. The switch uses the device identifier returned via the response combining logic to route the data transfer associated with the issued command.

US Patent:

6523080, Feb 18, 2003

Filed:

Jan 27, 1998

Appl. No.:

09/014090

Inventors:

Herman Lee Blackmon - Rochester MN
Robert Allen Drehmel - Goodhue MN
Lyle Edwin Grosbach - Rochester MN
Kent Harold Haselhorst - Byron MN
David John Krolak - Dodge Center MN
James Anthony Marcella - Rochester MN
Peder James Paulson - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1342

US Classification:

710305, 710306, 711127, 711147, 711157

Abstract:

A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

US Patent:

6526469, Feb 25, 2003

Filed:

Nov 12, 1999

Appl. No.:

09/439068

Inventors:

Robert Allen Drehmel - Goodhue MN
Kent Harold Haselhorst - Byron MN
Russell Dean Hoover - Rochester MN
James Anthony Marcella - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710306

Abstract:

A processor-memory bus comprises a command portion for transmitting addresses and commands, having a unidirectional input portion for transmitting commands to a central repeater unit, and a unidirectional broadcast portion for broadcasting commands from the repeater. The input portion comprises a plurality of links running from different devices, wherein each link is less than the full width of the broadcast bus portion. A command is transmitted over the input portion in a plurality of bus cycles, and broadcast over the broadcast portion in a single bus cycle. Since multiple input links connect to the central command repeater, it is possible to keep the broadcast bus full notwithstanding the fact that multiple bus cycles are required to transmit an individual command on the input portion. Preferably, the links are arranged hierarchically, from processors to local repeaters, from local repeaters to the central repeater, and back again. Preferably, the central repeater globally arbitrates the bus, and once the bus is granted, the command propagates along each link at pre-defined clock cycles from bus grant.

US Patent:

6532185, Mar 11, 2003

Filed:

Feb 23, 2001

Appl. No.:

09/792605

Inventors:

Jean Louis Calvignac - Cary NC
Peter Irma August Barri - Bonheiden, BE
Ivan Oscar Clemminck - St-Amandsberg, BE
Kent Harold Haselhorst - Byron MN
Marco C. Heddes - Raleigh NC
Joseph Franklin Logan - Raleigh NC
Bart Joseph Gerard Pauwels - Tessenderlo, BE
Fabrice Jean Verplanken - La Gaude, FR
Miroslav Vrana - Ghent, BE

Assignee:

International Business Machines Corporation - Armonk NY
Alcatel - Paris

International Classification:

G11C 800

US Classification:

36523003, 365221, 3652385

Abstract:

Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the âwriteâ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

US Patent:

6557069, Apr 29, 2003

Filed:

Nov 12, 1999

Appl. No.:

09/439189

Inventors:

Robert Allen Drehmel - Goodhue MN
Kent Harold Haselhorst - Byron MN
Russell Dean Hoover - Rochester MN
James Anthony Marcella - Rochester MN
George Wayne Nation - Eyota MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

710307, 710107, 709253

Abstract:

An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters (ARPs), and between the ARPs and a central repeater (ASW). A command propagates from a requesting device to its local ARP, to the ASW. From the ASW, the command is broadcast to all devices on the bus by transmitting to all ARPs or directly attached memory, and from the ARPs to the devices. Preferably, the ASW globally arbitrates the address bus, and all commands propagate at pre-defined clock cycles through the bus. Preferably, each device on the bus independently signals a response via a separate response link running directly to a global collector, which collects all responses and broadcasts a single system-wide response back to the devices. In the preferred embodiment, addresses/commands and data are transmitted on essentially separate paths having different topologies, and at different times, and are arbitrated separately. The data portion of the network comprises a set of bi-directional links from the processors to a local data switch unit (DSW).

US Patent:

6628662, Sep 30, 2003

Filed:

Nov 29, 1999

Appl. No.:

09/450792

Inventors:

Herman Lee Blackmon - Rochester MN
Robert Allen Drehmel - Goodhue MN
Kent Harold Haselhorst - Byron MN
James Anthony Marcella - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12413

US Classification:

370447, 370461, 370462, 710113, 710241

Abstract:

A method and system for arbitrating data transfers between devices connected via electronically isolated buses at a switch. In accordance with the method and system of the present invention, multiple arbitration controllers are interposed between devices and a switch to which the devices are connected, wherein each of the multiple arbitration controllers are effective to select a data transfer operation and detect collisions between said selected data transfer operations. The switch is enabled for any selected data transfer operations between which collisions are not detected. The switch is also enabled for only one of the selected data transfer operations between which collisions are detected. Any selected data transfer operations for which the switch is not enabled are deferred. The deferred data transfer operations are prioritized within the multiple arbitration controllers, such that for a subsequent selection of the deferred data transfer operations, the switch is enabled for the deferred data transfer operations.

US Patent:

6895482, May 17, 2005

Filed:

Sep 10, 1999

Appl. No.:

09/394011

Inventors:

Herman Lee Blackmon - Rochester MN, US
Robert Allen Drehmel - Goodhue MN, US
Kent Harold Haselhorst - Byron MN, US
James Anthony Marcella - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F012/00

US Classification:

711158, 711151, 710112, 710244

Abstract:

An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution. Memory commands of that type are selected for execution each subsequent cycle until a valid memory command of that type is no longer available, or until a predetermined number has been executed, or until a memory command of another type has higher priority.