Kenichi I Miura

US Patent:

42187478, Aug 19, 1980

Filed:

Jun 5, 1978

Appl. No.:

5/912451

Inventors:

Kenichi Miura - Saratoga CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

G06F 748
G06F 750

US Classification:

364716

Abstract:

An arithmetic and logic unit (ALU) formed by a small number of different types of basic cells suitable for cellular integration to form large scale integrated (LSI) semiconductor circuits. The arithmetic and logic unit is formed from a plurality of 1-bit ALU cells. Each ALU cell is formed by a plurality of cellular integrated basic cells where each ALU cell includes two data inputs, A and B, and responsively produces a data output, F. Each ALU cell has provision for some type of carry circuit, carry ripple or carry look-ahead. In a carry ripple example, the 1-bit ALU cells are of two basic types, an odd type and an even type. The carry-out from an odd type cell is connected as a carry-in to an even type cell and similarly, the carry-out of an even type cell is connected as a carry-in to an odd type cell. The arithmetic and logic unit is formed by a plurality of alternating odd and even 1-bit ALU cells.

US Patent:

41632117, Jul 31, 1979

Filed:

Apr 17, 1978

Appl. No.:

5/897132

Inventors:

Kenichi Miura - Saratoga CA

Assignee:

Fujitsu Limited

International Classification:

G06F 702
G06F 750
G06F 1110

US Classification:

3401462

Abstract:

A tree-type combinatorial logic circuit comprising a plurality of identical functional units which may be arranged to operate as an N-bit magnitude comparator, a carry generator for an N-bit adder, or a parity predictor for 2N-bit binary counter. Each of the units is provided with four input terminals and two output terminals. The units are arranged to form a binary tree. Each unit has an internal logic circuit which generates outputs of G. sub. K*l =G. sub. K VE. sub. K. multidot. g. sub. l and E. sub. K*l =E. sub. K. multidot. E. sub. l, where "V" and ". multidot. " denote Boolean OR and AND operations, respectively. The desired functions are provided at the output terminals of the unit in the final stage of the tree. The input signals to the units in the first stage of the tree depend on the applications of the circuit. When used as a magnitude comparator, the inputs are a. sub. i. multidot. b. sub.

US Patent:

44384270, Mar 20, 1984

Filed:

Jul 20, 1978

Appl. No.:

5/926950

Inventors:

Kenichi Miura - Saratoga CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H03K 1324

US Classification:

340347DD

Abstract:

Decoder and method utilizing logic circuitry for decoding multi-bit digital signals. An input decoder decodes subsets of the input signals to provide a plurality of intermediate signals which are selectively combined to provide output signals which represent a desired decoding of the input signals. The intermediate signals are applied to generally parallel bus lines which extend centrally of the substrate on which the decoder is constructed. The logic circuits are arranged in blocks along both sides of the bus lines, with all of the bus lines extending past all of the logic blocks, and conductors extending transversely of the bus lines carry the appropriate intermediate signals from the bus lines to the logic blocks.

US Patent:

42246806, Sep 23, 1980

Filed:

Jun 5, 1978

Appl. No.:

5/912452

Inventors:

Kenichi Miura - Saratoga CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

G06F 1110

US Classification:

364738

Abstract:

A parity prediction circuit for predicting parity in an adder, counter or similar device. The parity prediction is obtained with a parity prediction network connected from most significant bit to least significant bit. The parity prediction network is used in place of a parity generator or in combination with a parity generator for error checking purposes. In a special application, the parity prediction is employed for a ripple-carry type counter where the predicted parity bit is produced by a single network of NAND gates connected in series from high-order to low-order counter bits. The predicted parity is available no later than the completion of the carry-out propagation.