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Us Patents
Plasma Immersion Ion Implantation Process With Reduced Polysilicon Gate Loss And Reduced Particle Deposition
Kartik Santhanam - Fremont CA, US Peter I. Porshnev - San Jose CA, US Majeed A. Foad - Sunnyvale CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/425
US Classification:
438515, 438513, 257E21316, 257E21143
Abstract:
In plasma immersion ion implantation of a polysilicon gate, a hydride of the dopant is employed as a process gas to avoid etching the polysilicon gate, and sufficient argon gas is added to reduce added particle count to below 50 and to reduce plasma impedance fluctuations to 5% or less.
Reducing Photoresist Layer Degradation In Plasma Immersion Ion Implantation
Martin A. Hilkene - Gilroy CA, US Kartik Santhanam - Fremont CA, US Yen B. Ta - Cupertino CA, US Peter I. Porshnev - San Jose CA, US Majeed A. Foad - Sunnyvale CA, US
A method of plasma immersion ion implantation of a workpiece having a photoresist mask on its top surface prevents photoresist failure from carbonization of the photoresist. The method includes performing successive ion implantation sub-steps, each of the ion implantation sub-steps having a time duration over which only a fractional top portion of the photoresist layer is damaged by ion implantation. After each one of the successive ion implantation sub-steps, the fractional top portion of the photoresist is removed while leaving the remaining portion of the photoresist layer in place by performing an ashing sub-step. The number of the successive ion implantation sub-steps is sufficient to reach a predetermined ion implantation dose in the workpiece.
Kartik Ramaswamy - San Jose CA, US Kenneth S. Collins - San Jose CA, US Biagio Gallo - Palo Alto CA, US Hiroji Hanawa - Sunnyvale CA, US Majeed A. Foad - Sunnyvale CA, US Martin A. Hilkene - Gilroy CA, US Kartik Santhanam - Fremont CA, US Matthew D. Scotney-Castle - Morgan Hill CA, US
A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed.
Plasma Immersion Ion Implantation Process With Chamber Seasoning And Seasoning Layer Plasma Discharging For Wafer Dechucking
Manoj Vellaikal - Sunnyvale CA, US Kartik Santhanam - Fremont CA, US Yen B. Ta - Cupertino CA, US Martin A. Hilkene - Gilroy CA, US Matthew D. Scotney-Castle - Morgan Hill CA, US Canfeng Lai - Fremont CA, US Peter I. Porshnev - San Jose CA, US Majeed A. Foad - Sunnyvale CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/42
US Classification:
438513, 438473, 438514, 438528
Abstract:
In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to increased seasoning layer thickness. This is accomplished by first plasma-discharging residual electrostatic charge from the thick seasoning layer. The number of wafers which can be processed using the same seasoning layer is further increased by fractionally supplementing the seasoning layer after each wafer is processed, which may be followed by a brief plasma discharging of the supplemented seasoning before processing the next wafer.
Kartik Santhanam - Milpitas CA, US Martin A. Hilkene - Gilroy CA, US Manoj Vellaikal - Sunnyvale CA, US Mark R. Lee - Park City UT, US Matthew D. Scotney-Castle - Morgan Hill CA, US Peter I. Porshnev - Poway CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/22 H01L 21/38
US Classification:
438559, 438795, 257E2125
Abstract:
Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of doping a substrate may include forming a dopant region on a substrate by implanting one or more dopant elements into the dopant region of the substrate using a plasma doping process; forming a cap layer atop the dopant region; annealing the dopant region after forming the cap layer; and removing the cap layer after annealing the dopant region.
Safe Handling Of Low Energy, High Dose Arsenic, Phosphorus, And Boron Implanted Wafers
Majeed A. Foad - Sunnyvale CA, US Manoj Vellaikal - Sunnyvale CA, US Kartik Santhanam - Fremont CA, US
International Classification:
H01L 21/425
US Classification:
438513, 257E21473
Abstract:
A method of preventing toxic gas formation after an implantation process is disclosed. Certain dopants, when implanted into films disposed on a substrate, may react when exposed to moisture to form a toxic gas and/or a flammable gas. By in-situ exposing the doped film to an oxygen containing compound, dopant that is shallowly implanted into the layer stack reacts to form a dopant oxide, thereby reducing potential toxic gas and/or flammable gas formation. Alternatively, a capping layer may be formed in-situ over the implanted film to reduce the potential generation of toxic gas and/or flammable gas.
Plasma Immersion Ion Implantation Process With Chamber Seasoning And Seasoning Layer Plasma Discharging For Wafer Dechucking
Manoj Vellaikal - Sunnyvale CA, US Kartik Santhanam - Fremont CA, US Yen B. Ta - Cupertino CA, US Martin A. Hilkene - Gilroy CA, US Matthew D. Scotney-Castle - Morgan Hill CA, US Canfeng Lai - Fremont CA, US Peter I. Porshnev - San Jose CA, US Majeed A. Foad - Sunnyvale CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/62 G21K 5/10
US Classification:
438513, 25049221, 257E2152
Abstract:
In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to increased seasoning layer thickness. This is accomplished by first plasma-discharging residual electrostatic charge from the thick seasoning layer. The number of wafers which can be processed using the same seasoning layer is further increased by fractionally supplementing the seasoning layer after each wafer is processed, which may be followed by a brief plasma discharging of the supplemented seasoning before processing the next wafer.
Safe Handling Of Low Energy, High Dose Arsenic, Phosphorus, And Boron Implanted Wafers
Majeed A. Foad - Sunnyvale CA, US Manoj Vellaikal - Sunnyvale CA, US Kartik Santhanam - Fremont CA, US
International Classification:
H01L 21/263
US Classification:
438513, 257E21331
Abstract:
A method of preventing toxic gas formation after an implantation process is disclosed. Certain dopants, when implanted into films disposed on a substrate, may react when exposed to moisture to form a toxic gas and/or a flammable gas. By in-situ exposing the doped film to an oxygen containing compound, dopant that is shallowly implanted into the layer stack reacts to form a dopant oxide, thereby reducing potential toxic gas and/or flammable gas formation. Alternatively, a capping layer may be formed in-situ over the implanted film to reduce the potential generation of toxic gas and/or flammable gas.
Optical Design Verification and Test
Intel Corporation May 2016 - Nov 2016
Ic Reliability and Module Test Engineer
Cisco Jun 2015 - May 2016
Optical Design Verification and Test Engineer
George Mason University Aug 2013 - May 2014
Teaching Assistant
Bechtel Corporation Jun 2013 - Aug 2013
Control Systems Engineer
Education:
George Mason University 2009 - 2014
Master of Science, Masters, Electronics Engineering
University of Mumbai 2008 - 2012
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Hardwork Communication Skills Management Skills Pspice Vhdl Software Signal Processing Robotics Control Systems Design Statistics Hypothesis Testing Kinematics Matlab Statistical Inference Modelsim Embedded C Algorithms Verilog Image Processing Digital Signal Processors Simulations C Microcontrollers Labview Electrical Engineering C++ Java Linux Management Testing
Interests:
Reading Books Economic Empowerment Education Cricket Basketball Science and Technology Playing Video Games Football/Soccer E Sports Human Rights Learning About New Technologies Health
Bechtel Power Corporation Frederick, MD Jun 2013 to Aug 2013 Control Systems Engineer
Education:
George Mason University Fairfax, VA 2012 to 2014 MS in Electrical EngineeringKJ Somaiya College of Engineering Mumbai, Maharashtra 2008 to 2012 BS in Electronics Engineering
Bechtel Power Corporation Frederick, MD Jun 2013 to Aug 2013 Control Systems Engineer
Education:
George Mason University Fairfax, VA Aug 2012 to May 2014 MS in Electrical EngineeringUniversity of Mumbai Mumbai, Maharashtra Aug 2008 to May 2012 BS in Electronics Engineering
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