Joseph P Zelayeta

US Patent:

57990808, Aug 25, 1998

Filed:

Jul 13, 1995

Appl. No.:

8/502300

Inventors:

Gobi R. Padmanabhan - Sunnyvale CA
Joseph M. Zelayeta - Saratoga CA
Visvamohan Yegnashankaran - Redwood City CA
James W. Hively - Sunnyvale CA
John P. Daane - Saratoga CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H04L 900

US Classification:

380 4

Abstract:

A code mechanism is provided in an integrated circuit for identifying the integrated circuit such as by serial number or for use in enabling the circuit and equipment housing the circuit. Fuses, antifuses, and programmable field effect transistors are used in an array for establishing a code. The code can be established by loading a register through the array and then reading the register. Alternatively,the contents of the register can be compared with a code provided by a user to enable the circuit. In another embodiment, a ROM is loaded with a table of encryption keys, and a user addresses the ROM by loading an address in a register or in a RAM.