Joseph A Devore

US Patent:

6373094, Apr 16, 2002

Filed:

Jul 18, 2001

Appl. No.:

09/908024

Inventors:

Andrew Marshall - Dallas TX
Joseph A. Devore - Dallas TX
Ross E. Teggatz - McKinney TX
Wayne T. Chen - Plano TX
Ricky D. Jordanger - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29788

US Classification:

257315, 257314, 36518501

Abstract:

An EEPROM cell ( ) formed on a substrate ( ) using conventional process steps is provided. The cell ( ) includes first ( ) and second ( ) conductive regions in the substrate ( ) below the substrates outer surface ( ), and the first ( ) and second ( ) conductive regions are laterally displaced from one another by a predetermined distance ( ). The cell ( ) also includes an insulating layer ( ) outwardly from the outer surface ( ) of the substrate ( ) positioned so that its edges are substantially in alignment between the first ( ) and second ( ) conductive regions. The cell ( ) further includes a floating gate layer ( ) outwardly from the insulating layer ( ) and in substantially the same shape as the insulating layer ( ). The cell ( ) also includes a diffusion region ( or ) that extends laterally from at least one of the first ( ) and second ( ) conductive regions so as to overlap with the insulating layer ( ). The diffusion region ( or ) provides a source of charge for placement on the floating gate layer ( ) when programming the EEPROM cell ( ).

US Patent:

6373343, Apr 16, 2002

Filed:

Aug 28, 2000

Appl. No.:

09/649367

Inventors:

David J. Baldwin - Allen TX
Christopher M. Cooper - Denison TX
Joseph A. Devore - Richardson TX
Ross E. Teggatz - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03B 524

US Classification:

331 76, 331 60, 331 74, 331111, 331143

Abstract:

An integrated circuit ( ) is disclosed comprising a fundamental frequency oscillator comprising a reference node ( ) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node ( ). The integrated circuit ( ) also comprises a circuit (C ) coupled to the reference node. The circuit (C ) is operable to sense the voltage at the reference node ( ), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit ( ) also comprises logic ( ) coupled to the circuit (C ) and load circuitry ( ) coupled to the logic ( ). The logic ( ) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.

US Patent:

6376870, Apr 23, 2002

Filed:

Sep 8, 2000

Appl. No.:

09/658202

Inventors:

Joseph A. Devore - Richardson TX
Toru Tanaka - Dallas TX
Ross E. Teggatz - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2972

US Classification:

257288, 257369, 257371, 257391, 257500, 257550

Abstract:

A high-breakdown voltage transistor ( â) is disclosed. The transistor ( â) is formed into a well arrangement in which a shallow, heavily doped, well ( ) is disposed at least partially within a deeper, more lightly-doped well ( ), both formed into an epitaxial layer ( ) of the substrate ( ). The deep well ( ) is also used, by itself, for the formation of high-voltage transistors, while the shallower well ( ) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or âback-gate-to-substrateâ) junction breakdown.

US Patent:

6407626, Jun 18, 2002

Filed:

Nov 17, 2000

Appl. No.:

09/715759

Inventors:

Joseph A. Devore - Richardson TX
Tohru Tanaka - Dallas TX
Ross E. Teggatz - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 500

US Classification:

327552, 327554, 327337

Abstract:

Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.

US Patent:

6469884, Oct 22, 2002

Filed:

Dec 24, 1999

Appl. No.:

09/472710

Inventors:

Joseph A. Devore - Richardson TX
Reed Adams - Plano TX
Ross Teggatz - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 322

US Classification:

361111, 361104, 365 7, 327525

Abstract:

An integrated circuit ( ) having at least one programmable fuse (F ) and ESD circuitry (MN , MN ) preventing the fuse (F ) from being unintentionally blown when a voltage transient exists on a main voltage potential (V ). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MN ) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.

US Patent:

6476667, Nov 5, 2002

Filed:

Oct 24, 1997

Appl. No.:

08/959959

Inventors:

Ross Elliot Teggatz - Dallas TX
Joseph Allen Devore - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 110

US Classification:

327538, 327543, 327427

Abstract:

A circuit and method are provided for accurate and adjustable current limiting/sensing in a power IC ( ). In particular, a current limiting/sensing circuit ( ) and method of use are provided that substitutes a transistor (MD ) in place of a resistor. Consequently, all of the components (MD , MD , MD ) in the IC ( ) may be identical transistors, which may be fabricated by one process and integrated in one power structure. Therefore, process variations from device to device and errors due to thermal gradients between components may be minimized, thereby reducing the complexity and fabrication costs of the power ICs. Additionally, a user may readily adjust the trip/sensing point of the current limiting circuit ( ) without having to physically alter individual components in the IC ( ).

US Patent:

6486740, Nov 26, 2002

Filed:

Aug 28, 2000

Appl. No.:

09/651568

Inventors:

David J. Baldwin - Allen TX
Ross E. Teggatz - McKinney TX
Joseph A. Devore - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 114

US Classification:

330292, 330107, 330294

Abstract:

One aspect of the invention is an integrated circuit ( or ) comprising an amplifier ( or ) having at least two poles in its frequency response and an output impedance compensation circuit (M A, M M AC or M A, M M M AC ) coupled to an output node ( ) of the amplifier ( or ). The output impedance compensation circuit (M A, M M AC or M A, M M M AC ) is operable to create a feedback signal proportional to the impedance of an output load ( ) coupled to the output node ( ), and create a zero in the frequency response of the amplifier ( or ) in response to the feedback signal between the at least two poles.

US Patent:

6940131, Sep 6, 2005

Filed:

Jun 30, 2003

Appl. No.:

10/609920

Inventors:

David John Baldwin - Allen TX, US
Joseph A. Devore - Richardson TX, US
Robert Steinhoff - Dallas TX, US
Jonathan Brodsky - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L023/62

US Classification:

257355, 257127, 257170, 257356, 257360, 257409, 257452, 257484, 257605

Abstract:

The present invention includes a MOS device () that has a P-type substrate () and an N-type drain region () formed within the substrate (). An annular N-type source region () generally surrounds the drain region (). The source region () serves as both the source for the MOS device () and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region () generally surrounds the drain region () and is electrically insulated from the drain region () and electrically connected to the source region (). An annular P-type bulk region () generally surrounds the source region () and is electrically connected to the source region ().