John E Schafer

Author:

John C. Schafer

ISBN #:

0938692666

Author:

John W. Schafer

ISBN #:

0471017108

Author:

John R. Schafer

ISBN #:

0398074437

Author:

John R. Schafer

ISBN #:

0398074445

US Patent:

60731583, Jun 6, 2000

Filed:

Jul 29, 1993

Appl. No.:

8/099083

Inventors:

Robert Marshall Nally - Plano TX
John Charles Schafer - Wylie TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1300

US Classification:

709102

Abstract:

A system and method for time slicing multiple received data streams utilizing multiple processors in such a manner as to ensure that all processors are running at full capability and are efficiently timesharing a global memory storage area. The received data streams are each divided into fixed portions called spans. The invention is operable for sequencing the movement of the time-sliced spans between the processors, adjusting the scheduling of particular ones of the time-sliced spans as a function of either processor availability or maintenance of real-time transmission of the received real-time time-sliced data streams.

US Patent:

54406838, Aug 8, 1995

Filed:

Oct 20, 1994

Appl. No.:

8/328382

Inventors:

Robert M. Nally - Plano TX
John C. Schafer - Wylie TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1500

US Classification:

395162

Abstract:

A digital video editor employing a single chip special-purpose digital video processing unit (VPU) having the capability to combine several different digital video input signals into a single digital video output signal is disclosed. The VPU comprises a microprocessor operating under a set of instructions which is operative for receiving, storing and manipulating portions of an incoming digital video signal and a delay circuit, coupled to the microprocessor, for delaying execution of a particular instruction if a particular portion upon which the instruction is to operate has not yet been stored. The VPU processes multiple digitized video signals in real time in a time-sharing fashion because its processing speed is substantially greater than the rate at which it receives video data and processes multiple picture elements of a single digital stream simultaneously. In a preferred environment, The VPU operates in conjunction with an IBM compatible personal computer, an inexpensive general purpose computer. By processing video digitally, the VPU avoids generation loss and allows efficient digital compression and storage of video data.

US Patent:

58219188, Oct 13, 1998

Filed:

Mar 13, 1995

Appl. No.:

8/402862

Inventors:

Christopher Lloyd Reinert - Plano TX
Sudhir Sharma - Plano TX
Robert Marshall Nally - Plano TX
John Charles Schafer - Wylie TX

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

G09G 504

US Classification:

345154

Abstract:

A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

US Patent:

56253796, Apr 29, 1997

Filed:

Mar 13, 1995

Appl. No.:

8/402935

Inventors:

Christopher L. Reinert - Plano TX
Sudhir Sharma - Plano TX
Robert M. Nally - Plano TX
John C. Schafer - Wylie TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 504

US Classification:

345154

Abstract:

A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

US Patent:

55772030, Nov 19, 1996

Filed:

Mar 13, 1995

Appl. No.:

8/402934

Inventors:

Christopher L. Reinert - Plano TX
Sudhir Sharma - Plano TX
Robert M. Nally - Plano TX
John C. Schafer - Wylie TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 500

US Classification:

345200

Abstract:

Methods are provided for transferring a stream of video data from a video data source to a display interface unit 20. A video data word is clocked into a first-in-first-out memory 30 by a first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

US Patent:

55066046, Apr 9, 1996

Filed:

Apr 6, 1994

Appl. No.:

8/223845

Inventors:

Robert M. Nally - Plano TX
John C. Schafer - Wylie TX
Jeffrey A. Niehaus - Dallas TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 504

US Classification:

345154

Abstract:

A processing system 100 is provided which includes a memory 107 and memory control circuitry 203. Packing circuitry 215 is operable to receive a stream of video data words in a first YUV format and convert those video data words into a plurality of packed words in a second YUV format. Memory control circuitry 203 is operable to simultaneously store the plurality of packed YUV words in memory 107 in the second format along with a plurality of RGB words.

US Patent:

55812805, Dec 3, 1996

Filed:

Mar 13, 1995

Appl. No.:

8/402931

Inventors:

Christopher L. Reinert - Plano TX
Sudhir Sharma - Plano TX
Robert M. Nally - Plano TX
John C. Schafer - Wylie TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G09G 500

US Classification:

345200

Abstract:

A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

US Patent:

55985254, Jan 28, 1997

Filed:

Jan 23, 1995

Appl. No.:

8/376919

Inventors:

Robert M. Nally - Plano TX
John C. Schafer - Wylie TX

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 1500

US Classification:

395520

Abstract:

A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.

Address:

1370 W 104 Pl, Northglenn, CO 80234

VIN:

1B3HB28B67D198120

Make:

DODG

Model:

CALI

Year:

2007