Carnegie Mellon University 1997 - 2002
Doctorates, Doctor of Philosophy, Computer Engineering
University of Pittsburgh 1995 - 1997
Master of Science, Masters, Electrical Engineering
Tsinghua University 1990 - 1995
Bachelors, Bachelor of Science, Engineering
Skills:
Semiconductors Ic Mixed Signal Soc Asic Cmos Analog Analog Circuit Design Verilog Vlsi Circuit Design Debugging Fpga Embedded Software Rtl Design Embedded Systems Eda Digital Signal Processors Integrated Circuit Design Rf Firmware
Us Patents
Multi-Protocol Radio Frequency Identification Transceiver
Jiangfeng Wu - Aliso Viejo CA, US Donald Edward Major - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04Q 5/22
US Classification:
340 101, 3405721, 340 103, 341155, 375316, 375346
Abstract:
A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.
Multi-Protocol Radio Frequency Identification Transponder Tranceiver
A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.
Multi-Protocol Radio Frequency Identification Transceiver
Jiangfeng Wu - Aliso Viejo CA, US Donald Edward Major - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 1/16
US Classification:
455336, 455338, 455215, 340 101, 340 103, 3405721
Abstract:
A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.
Jiangfeng Wu - Aliso Viejo CA, US Tianwei Li - Irvine CA, US Arnoldus Venes - Laguna Niguel CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04M 1/00
US Classification:
37939901, 379394
Abstract:
A line driver comprises a driving amplifier receiving an input of the line driver, a current sense resistor connected between the driving amplifier output and the line driver output, and a feedback amplifier sensing the voltage across the current sense resistor and providing a corresponding feedback voltage that is proportional to the output current to the driving amplifier, thereby determining an output impedance at the line driver output. Precise output impedance can be realized by using a high precision resistor as the current sense resistor, and using resistive feedback amplifiers with accurate gains as the driving and feedback amplifiers. The resistance of the current sense resistor can be substantially less than the line driver output impedance, and the driving amplifier output voltage swing can be substantially less than twice the line driver output voltage swing.
Jiangfeng Wu - Aliso Viejo CA, US Donald Edward Major - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 1/16
US Classification:
455336, 455338, 455215, 340 101, 340 103, 3405721
Abstract:
A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.
System Including Adaptive Power Rails And Related Method
Chun-Ying Chen - Irvine CA, US Jiangfeng Wu - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G05F 1/10
US Classification:
327535
Abstract:
According to one disclosed embodiment, an adaptive voltage rail circuit for integrating low voltage devices with high voltage analog circuits is described. This adaptive voltage rail circuit includes a high voltage analog circuit having a common mode voltage. Further included is a first voltage rail having a first rail voltage which is based on and greater than the common mode voltage of the high voltage analog circuit. A second voltage rail having a second rail voltage which is based on and less than the same common mode voltage is also present. By connecting these first and second voltage rails across at least one low voltage device, an adaptive voltage rail circuit is able to safely integrate low voltage devices with high voltage analog circuits in the same system.
Patrick Teterud - Plano TX, US Jiangfeng Wu - Pittsburgh PA, US Thomas Eaton - Wylie TX, US
International Classification:
H03B001/00
US Classification:
327/110000
Abstract:
An ultra-fast drive circuit () providing a rail-to-rail drive voltage at an output node (N). A pair of bipolar output transistors (Q, Q) are selectively driven via a FET drive circuit (), and by a control circuit () to achieve a rail-to-rail output voltage (V-V) that is very fast. The drive FETs comprise three serially connected FETs (M, M, M) whereby the middle FET (M) is the control FET effecting the control of the output transistors (Q, Q). The other two FETs (M, M) are always in the on state and complete either the pull-up or pull-down of the voltage at the output node (N), depending on the state of the middle FET (M). The control FETs () provide two output control signals () to the output transistors (Q, Q), with the control line () controlling the state of the middle switching FET (M).
Low Power Programmable Reset Pump For Cmos Imagers
Jiangfeng Wu - Aliso Viejo CA, US Jiafu Luo - Irvine CA, US
International Classification:
H04N 5/335
US Classification:
348308000
Abstract:
There is provided a circuit comprising a plurality of pixels arranged in rows and columns, a charge pump having a first input voltage and a second input voltage and having at least one output, at least one reset driver operatively connected to each row of the pixels, wherein the at least output of the charge pump provides a first reset voltage to at least one row of pixels at a first time and provides a second reset voltage to at least one row of other pixels at a second time. The charge pump may include a capacitor selectively connected to the first input voltage and the second input voltage, whereon the capacitor accumulates a boosted voltage.
Name / Title
Company / Classification
Phones & Addresses
Jiangfeng Wu Xt 66198
Broadcom Corporation Semiconductors and Related Devices
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