Jeffrey A Hawkey

US Patent:

53434781, Aug 30, 1994

Filed:

Nov 27, 1991

Appl. No.:

7/800901

Inventors:

Larry C. James - West Columbia SC
Carl W. Kagy - Lexington SC
Jeffrey F. Gates - Newberry SC
Jeffrey A. Hawkey - Easley SC
Thomas F. Heil - Easley SC
David L. Simpson - West Columbia SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G01R 3128

US Classification:

371 223

Abstract:

System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. These registers are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers and accessible therethrough. The introduction of memory into the serial test bus permits configuration information to be stored in the modules and/or integrated circuits making up the computer system. If memory and/or other devices external to the serial test bus are included on modules or other components of the system, the time required to access these devices may exceed a default access time defined by the operating speed of the serial test bus.

US Patent:

6098113, Aug 1, 2000

Filed:

Apr 6, 1995

Appl. No.:

8/417701

Inventors:

Thomas F. Heil - Easley SC
Edward A. McDonald - Lexington SC
James M. Ottinger - Columbia SC
Jeffrey A. Hawkey - Easley SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 300

US Classification:

710 1

Abstract:

Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.

US Patent:

61417114, Oct 31, 2000

Filed:

Dec 19, 1996

Appl. No.:

8/769998

Inventors:

Pranay D. Shah - Fremont CA
Kenneth C. Ma - Cupertino CA
Jeffrey A. Hawkey - Morgan Hill CA
Kenneth J. Kotlowski - Easley SC

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710103

Abstract:

A secondary bus controller allows for hot insertion and ejection of devices from the secondary bus without ceasing operations or halting software in the host computer. When a device is to be inserted a signal is sent to the secondary bus controller. The secondary bus controller suspends operation of the secondary bus, placing devices on the secondary bus in stasis. An interrupt handler reconfigures the system for the newly inserted card once it has been inserted. Attempts to access devices on the secondary bus during the insertion process may be met with a retry signal until insertion is complete. The ejection process follows similar steps, isolating and suspending operations on the secondary bus and triggering an interrupt routine in the host processor to reconfigure the system. The host processor and primary busses, along with the secondary bus controller remain active throughout the insertion or ejection processes. Thus, applications running on the host computer need not be terminated during insertion or ejection.