Jeanna M Matthews from 225 County Route 43, Massena Center, NY 13662, age 53

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Position:

Associate Professor at Clarkson University

Location:

Massena, New York

Industry:

Computer & Network Security

Work:

Clarkson University since 2000
Associate Professor

Education:

University of California, Berkeley 1994 - 1999
PhD, Computer Science Columbus School for Girls

Method And System To Adjust Non-Volatile Cache Associativity
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US Patent:

7127571, Oct 24, 2006
Filed:

Dec 30, 2003
Appl. No.:

10/750040
Inventors:

Andrew S. Grover - Beaverton OR, US
Jeanna N. Matthews - Massena NY, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/16
US Classification:

711156, 711100, 711102, 711103, 711111, 711113, 711114, 711128, 713300, 713320, 713330, 713340
Abstract:

A method and system to adjust a non-volatile cache associativity are described. In one embodiment, the method and system include determining a status of the system; and setting an associativity level of the non-volatile memory cache (NVC) of the system, based on that status of the system. In one embodiment, the non-volatile memory unit is a cache of the hard disk. Furthermore, in one embodiment, determining the status of the system includes determining whether the system is a mobile computer, and if so, determining whether the system is receiving power from a battery source or AC power from a wall outlet.

Preventing Storage Of Streaming Accesses In A Cache
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US Patent:

7360015, Apr 15, 2008
Filed:

May 4, 2004
Appl. No.:

10/838435
Inventors:

Jeanna N. Matthews - Massena NY, US
John I. Garney - Portland OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 13/00
US Classification:

711113, 711138
Abstract:

In one embodiment of the present invention, a method may include determining whether requested information is part of a streaming access, and directly writing the requested information from a storage device to a memory if the requested information is part of the streaming access. Alternately, if the requested information is not part of the streaming access, it may be written from the storage device to a cache. In various embodiments, the cache may be a non-volatile disk cache.

Method, Device, And System To Avoid Flushing The Contents Of A Cache By Not Inserting Data From Large Requests
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US Patent:

7401188, Jul 15, 2008
Filed:

Jun 29, 2005
Appl. No.:

11/172051
Inventors:

Jeanna N. Matthews - Massena NY, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/00
US Classification:

711138, 711118, 711152, 711170, 711173
Abstract:

A method, device, and system are disclosed. In one embodiment, the method comprises setting a threshold length for data allowed in a cache, inserting data into the cache during a read or a write request if the length of the data requested is less than the threshold length, and not inserting data into the cache during a read or write request if the length of the data requested is greater than or equal to the threshold length.

Maintaining Disk Cache Coherency In Multiple Operating System Environment
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US Patent:

7558911, Jul 7, 2009
Filed:

Dec 18, 2003
Appl. No.:

10/739254
Inventors:

John I. Garney - Portland OR, US
Jeanna N. Matthews - Massena NY, US
Kirk D. Brannock - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/06
US Classification:

711113, 711205
Abstract:

Processor-based systems may use more than one operating system and may have disk drives which are cached. Systems which include a write-back cache and a disk drive may develop incoherent data when operating systems are changed or when disk drives are removed. Scrambling a partition table on a disk drive and storing cache identification information may improve data coherency in a processor-based system.

Method And Apparatus To Maintain Data Integrity In Disk Cache Memory During And After Periods Of Cache Inaccessibility
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US Patent:

7627713, Dec 1, 2009
Filed:

Dec 29, 2005
Appl. No.:

11/321434
Inventors:

Sanjeev N. Trika - Hillsboro OR, US
Michael K. Eschmann - Lees Summit MO, US
Jeanna N. Matthews - Massena NY, US
Vasudevan Srinivasan - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/00
US Classification:

711113, 711135
Abstract:

A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.

Maintaining Write Ordering In A System
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US Patent:

7640395, Dec 29, 2009
Filed:

Mar 30, 2006
Appl. No.:

11/394364
Inventors:

Richard L. Coulson - Portland OR, US
Sanjeev N. Trika - Hillsboro OR, US
Jeanna N. Matthews - Massena NY, US
Robert W. Faber - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/00
US Classification:

711113, 711135, 711206
Abstract:

In one embodiment, the present invention includes a method for maintaining a sequence of writes into a disk cache, where the writes correspond to disk write requests stored in the disk cache, and ordering cache writes from the disk cache to a disk drive according to the sequence of writes. In this way, write ordering from an operating system to a disk subsystem is maintained. Other embodiments are described and claimed.

Technique To Write To A Non-Volatile Memory
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US Patent:

7797479, Sep 14, 2010
Filed:

Jun 30, 2005
Appl. No.:

11/172608
Inventors:

Sanjeev N. Trika - Hillsboro OR, US
Robert W. Faber - Hillsboro OR, US
Rick Coulson - Portland OR, US
Jeanna N. Matthews - Massena NY, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 13/00
G06F 13/28
G06F 9/26
G06F 9/34
US Classification:

711103, 711202, 711E12103
Abstract:

A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

Dynamically Adjusting Cache Policy Based On Device Load In A Mass Storage System
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US Patent:

7886110, Feb 8, 2011
Filed:

Dec 27, 2007
Appl. No.:

11/965652
Inventors:

Jeanna N. Matthews - Massena NY, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/00
US Classification:

711113, 711118
Abstract:

A dynamic cache policy manager for a mass memory may be used to decide whether a data request is to be routed to the cache or directly to the mass memory, based on estimated delays in processing the request. The choice may be based, at least partially, on the size of the respectively queues for the cache and mass memory. For write requests, the choice may be based on how many erase blocks are available in the cache.