James L Petivan

US Patent:

6349391, Feb 19, 2002

Filed:

Oct 27, 1999

Appl. No.:

09/428701

Inventors:

James L. Petivan - Palo Alto CA
Jonathan K. Lundell - Half Moon Bay CA
Don C. Lundell - Boulder Creek CA

Assignee:

Resilience Corporation - Sunnyvale CA

International Classification:

G06F 1100

US Classification:

714 11, 712 10

Abstract:

A redundant clock system for use in a computer is provided including a first oscillator which produces first reference clock signals; a second oscillator which produces second reference clock signals; a third oscillator which produces third reference clock signals; a first multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a second multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a third multiplexer which receives the first, second and third reference clock signals from the first, second and third oscillators and which provides a designated one of the received reference clock signals as a selected reference clock signal; a first phase-locked loop (PLL) circuit coupled in a first feedback circuit in which the first PLL receives as reference input the selected reference clock signal provided by the first multiplexer and receives as feedback input a first output clock signal; a second phase-locked loop (PLL) circuit coupled in a second feedback circuit in which the second PLL receives as reference input the selected reference clock signal provided by the second multiplexer and which receives as feedback input the a second output clock signal; a third phase-locked loop (PLL) circuit coupled in a third feedback circuit in which the third PLL receives as reference input the selected reference clock signal provided by the third multiplexer and receives as feedback input a third output clock signal; and a reference clock designation unit which determines whether any one of the first, second or third reference clock signals has failed and which designates one of the two other reference clock signals in the event that one of the reference clock signals has failed.

US Patent:

49356143, Jun 19, 1990

Filed:

Apr 5, 1989

Appl. No.:

7/333637

Inventors:

James E. Hubbard - Derry NH
James L. Petivan - New Orleans LA

Assignee:

The Charles Stark Draper Laboratory, Inc. - Cambridge MA

International Classification:

G01J 120

US Classification:

2502011

Abstract:

The present invention is a two beam, double pass, phase shifting interferometric system for characterizing the phase profile of a radiation path. In the preferred form of the invention, a monochromatic beam is split into a reference beam and a test path beam. The test path beam is directed toward a fixed reflector which in turn directs that beam to the image sensor with a fixed length in the direction of propagation. The reference beam is directed to a movable reflector which directs that beam also to the image sensor, while introducing phase modulation. The system provides a measure of phase offset introduced into the reference beam at times of minimum or maximum intensity as measured by each photo detector in the image sensor, as the phase modulation of the reference beam is stepped over one complete wavelength. The phase profile of the test path is constructed using the accurate representation of the modulating refelector's position at the measured minimum or maximum intensity and the number of discontinuities in the phase offset data at each element's location.

US Patent:

61417696, Oct 31, 2000

Filed:

May 9, 1997

Appl. No.:

8/853670

Inventors:

James L. Petivan - Palo Alto CA
Jonathan K. Lundell - Half Moon Bay CA
Don C. Lundell - Boulder Creek CA

Assignee:

Resilience Corporation - Palo Alto CA

International Classification:

G06F 1100

US Classification:

714 10

Abstract:

A fault tolerant computer system is provided which includes a first system module with a first processor and a first processor bus and a first I/O bus; a second system module with a second processor and a second processor bus and a second I/O bus; a third system module with a third processor and a third processor bus and a third I/O bus; wherein the first system module further includes a first control device which coordinates transfer of first transaction information between the first processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the first system module includes first comparison logic which compares first transaction information with corresponding second transaction information; wherein the second system module further includes a second control device which coordinates transfer of second transaction information between the second processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the second system module includes second comparison logic which compares second transaction information with corresponding third transaction information; wherein the third system module further includes a third control device which coordinates transfer of third transaction information between the third processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the third system module includes third comparison logic which compares third transaction information with corresponding first transaction information; and transfer circuitry which transfers the first, second and third transaction information among the first, second and third system modules.

US Patent:

62405268, May 29, 2001

Filed:

Oct 27, 1999

Appl. No.:

9/428869

Inventors:

James L. Petivan - Palo Alto CA
Jonathan K. Lundell - Half Moon Bay CA
Don C. Lundell - Boulder Creek CA

Assignee:

Resilience Corporation - Palo Alto CA

International Classification:

G06F 1100

US Classification:

714 11

Abstract:

A fault tolerant computer system is provided which includes a first system module with a first processor and a first processor bus and a first I/O bus; a second system module with a second processor and a second processor bus and a second I/O bus; a third system module with a third processor and a third processor bus and a third I/O bus; wherein the first system module further includes a first control device which coordinates transfer of first transaction information between the first processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the first system module includes first comparison logic which compares first transaction information with corresponding second transaction information; wherein the second system module further includes a second control device which coordinates transfer of second transaction information between the second processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the second system module includes second comparison logic which compares second transaction information with corresponding third transaction information; wherein the third system module further includes a third control device which coordinates transfer of third transaction information between the third processor bus and each of the first I/O bus or the second I/O bus or the third I/O bus; and wherein the third system module includes third comparison logic which compares third transaction information with corresponding first transaction information; and transfer circuitry which transfers the first, second and third transaction information among the first, second and third system modules.