Howard D Bartlow

US Patent:

6525423, Feb 25, 2003

Filed:

Jun 19, 2001

Appl. No.:

09/884788

Inventors:

Howard D. Bartlow - Nampa ID

Assignee:

Cree Microwave, Inc. - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

257737, 257738, 257778

Abstract:

An inexpensive method of providing uniform and consistent spacing between a semiconductor die and a supporting substrate includes providing relatively rigid spacers such as a plurality of lengths of wires or a plurality of bumps on the mounting surface for the chip. The spacers allow a uniform desired spacing of the die from the supporting substrate when attached by an epoxy.

US Patent:

6548869, Apr 15, 2003

Filed:

Jul 13, 2001

Appl. No.:

09/905294

Inventors:

Kenneth P. Brewer - Mountain View CA
Howard D. Bartlow - Nampa ID
Johan A. Darmawan - Santa Clara CA

Assignee:

Cree Microwave, Inc. - Sunnyvale CA

International Classification:

H02H 900

US Classification:

257355, 257356, 257296

Abstract:

An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

US Patent:

7132701, Nov 7, 2006

Filed:

Jul 27, 2001

Appl. No.:

09/682151

Inventors:

Martin E. Kordesch - The Plains OH, US
Howard D. Bartlow - Nampa ID, US
Richard L Woodin - Austin TX, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 29/737
H01L 21/331

US Classification:

257198, 438318, 257E29188, 257E21371, 257E21541

Abstract:

Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

US Patent:

7638820, Dec 29, 2009

Filed:

Nov 6, 2006

Appl. No.:

11/556967

Inventors:

Martin E. Kordesch - The Plains OH, US
Howard D. Bartlow - Nampa ID, US
Richard L. Woodin - Austin TX, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 29/737
H01L 21/331

US Classification:

257198, 257192, 257193, 257194, 257195, 257196, 257197, 257199, 257200, 257201, 257743, 257744, 257745, 257E29188, 257E21371, 257E21541, 438309, 438312, 438313, 438314, 438315, 438316, 438317

Abstract:

Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the, same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

US Patent:

RE42423, Jun 7, 2011

Filed:

Nov 7, 2008

Appl. No.:

12/266739

Inventors:

Martin E. Kordesch - The Plains OH, US
Howard D. Bartlow - Nampa ID, US
Richard L. Woodin - Gorham ME, US

Assignee:

Fairchild Semiconductor Corporation - San Jose CA

International Classification:

H01L 29/737
H01L 21/331

US Classification:

257198, 257E29188, 257E21371, 257E21541, 438318

Abstract:

Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.