Hongwen W Gao

US Patent:

7209994, Apr 24, 2007

Filed:

Feb 25, 2005

Appl. No.:

11/066019

Inventors:

Alexander C. Klaiber - Mountain View CA, US
Hongwen Gao - Union City CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 13/24
G06F 9/45

US Classification:

710264, 710260, 710262, 710269, 719324

Abstract:

In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is configured to initiate the virtual interrupt responsive to the interrupt state. In another embodiment, a method comprises storing an interrupt state describing a virtual interrupt in a storage area allocated to a guest. A processor initiates the virtual interrupt subsequent to initiating execution of the guest, responsive to the interrupt state. In still another embodiment, a computer accessible medium stores a plurality of instructions comprising instructions which, when executed on a processor in response to a physical interrupt: determine a guest into which a virtual interrupt corresponding to the physical interrupt is to be injected; and store an interrupt state describing the virtual interrupt in a storage area allocated to the guest.

US Patent:

7937700, May 3, 2011

Filed:

Feb 25, 2005

Appl. No.:

11/065777

Inventors:

Alexander C. Klaiber - Mountain View CA, US
Michael Shawn Greske - Fremont CA, US
Hongwen Gao - Union City CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9/455
G06F 9/46
G06F 13/00
G06F 7/38

US Classification:

718 1, 718108, 711106, 712228

Abstract:

In one embodiment, a processor comprises a plurality of registers configured to store processor state and an execution core coupled to the registers. The execution core is configured, during a switch between processor execution of a guest and processor execution of a virtual machine manager (VMM) that controls the guest, to save only a portion of the processor state to a memory. In another embodiment, a method comprises switching from processor execution of a first one of a guest and a virtual machine manager (VMM) to processor execution of a second one of the guest and the VMM, wherein the VMM controls execution of the guest; and during the switching, the processor saving only a portion of a processor state to memory.

US Patent:

8127098, Feb 28, 2012

Filed:

Feb 25, 2005

Appl. No.:

11/066873

Inventors:

Alexander C. Klaiber - Mountain View CA, US
Kevin J. McGrath - Los Gatos CA, US
Hongwen Gao - Union City CA, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

G06F 12/14

US Classification:

711163, 711205, 711151

Abstract:

In one embodiment, a processor is configured to operate in a first mode in which privilege level protection is disabled and paging is enabled. In another embodiment, a method is contemplated including intercepting a write to a control register by a guest executing in a processor; determining that the write attempts to establish a first mode in the processor in which privilege level protection is disabled and paging is disabled; and causing the guest to execute in a second mode in which privilege level protection is disabled and paging is enabled instead of the first mode. A computer accessible medium comprising instruction implementing at least a portion of the method is also described.

US Patent:

6898697, May 24, 2005

Filed:

Mar 29, 2002

Appl. No.:

10/113387

Inventors:

Hongwen Gao - Union City CA, US
Chetana N. Keltcher - Sunnyvale CA, US
Michael T. Clark - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F009/52
G06F012/02
G06F013/00

US Classification:

712229, 712219, 712225, 711201, 711208, 711209, 710 33

Abstract:

A processor is configured to operate in a modes which utilize segmentation and which do not utilize segmentation. The processor includes circuitry which is configured to detect and respond to mode and state changes. The circuitry is configured to determine whether a segmentation state of the processor changes in response to execution of a control transfer operation. If the segmentation state does not change as a result of the transfer instruction, execution of instructions may continue sequentially and a corresponding first check performed. However, if the segmentation state does change as a result of the transfer instruction, a flush of the pipeline is initiated prior to performing a corresponding second check. When a first mode of operation is detected a limit check may be performed, while a canonical check may performed when a second mode of operation is detected. A special register is defined which is configured to indicate changes in segmentation state subsequent to a control transfer operations.

US Patent:

20190361699, Nov 28, 2019

Filed:

May 22, 2018

Appl. No.:

15/986626

Inventors:

- Santa Clara CA, US
Magiting Talisayon - West Newton MA, US
Hongwen Gao - Fremont CA, US
Benjamin Floering - San Jose CA, US
Emil Talpes - San Mateo CA, US

International Classification:

G06F 9/30

Abstract:

Systems, apparatuses, and methods for implementing a fastpath microcode sequencer are disclosed. A processor includes at least an instruction decode unit and first and second microcode units. For each received instruction, the instruction decode unit forwards the instruction to the first microcode unit if the instruction satisfies at least a first condition. In one implementation, the first condition is the instruction being classified as a frequently executed instruction. If a received instruction satisfies at least a second condition, the instruction decode unit forwards the received instruction to a second microcode unit. In one implementation, the first microcode unit is a smaller, faster structure than the second microcode unit. In one implementation, the second condition is the instruction being classified as an infrequently executed instruction. In other implementations, the instruction decode unit forwards the instruction to another microcode unit responsive to determining the instruction satisfies one or more other conditions.