Hoang Lv Tran

US Patent:

20080003224, Jan 3, 2008

Filed:

Jan 29, 2007

Appl. No.:

11/699733

Inventors:

Timothy Fong - Moraga CA, US
Varghese Palath - Fremont CA, US
R. Tesi - Berkeley CA, US
Hoang Tran - Menlo Park CA, US
Irving Weissman - Stanford CA, US

Assignee:

Cellerant Therapeutics, Inc. - San Carlos CA

International Classification:

A61K 39/395
A61K 39/00
A61P 35/00
C07K 16/00
C12N 5/00
C12P 21/08

US Classification:

424139100, 424173100, 435346000, 435375000, 530387100, 530387300

Abstract:

The disclosure relates to antibodies immunoreactive with CD45RA+ hematopoietic tumor cells (HTCs), hybridomas producing such antibodies, and methods of using the antibodies, particularly as therapeutic treatments for conditions or diseases characterized by CD45RA+ HTCs.

US Patent:

58215832, Oct 13, 1998

Filed:

Mar 6, 1996

Appl. No.:

8/610563

Inventors:

Fwu-Iuan Hshieh - Saratoga CA
Lih-Ying Ching - Cupertino CA
Hoang Tran - San Jose CA
Mike F. Chang - Cupertino CA

Assignee:

Siliconix incorporated - Santa Clara CA

International Classification:

H01L 2978

US Classification:

257330

Abstract:

A trenched DMOS transistor has significantly reduced on-resistance. A lightly doped P tub is formed surrounding the P+ body region in order to enhance avalanche breakdown. Thus the epitaxial layer resistivity can be decreased to reduce device on-resistance, while the desired breakdown voltage is also achieved. The on-resistance is further reduced by adding a pre-initial oxidation implant, i. e. phosphorous for an N channel device or boron for a P channel device. This forms a more heavily doped JFET or pinch region at the bottom of the trench and in the upper portion of the drift region. This N JFET region (which is P doped for a P channel device) is more heavily doped than the underlying epitaxial layer and surrounds the trench bottom, thus reducing on-resistance by increasing local doping concentration where otherwise a parasitic JFET would be present.