Harry W Scrivener

US Patent:

60732164, Jun 6, 2000

Filed:

Nov 25, 1997

Appl. No.:

8/980882

Inventors:

Edward A. McDonald - Baton Rouge LA
James M. Ottinger - Duluth GA
Harry W. Scrivener - Columbia SC

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711141

Abstract:

There is disclosed a memory control circuit for use in a processing system containing a plurality of processors coupled to a main memory by a common bus. The memory control circuit is adapted for implementing directory-based coherency in the processing system according to a selected coherency algorithm and comprises: 1) monitoring circuitry for detecting coherency corruption in a coherency directory associated with the main memory; and 2) coherency control circuitry responsive to a detection of coherency corruption in the coherency directory for dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner. In some embodiments, the monitoring circuitry further detects possible system coherency failure conditions external to the coherency directory and the coherency control circuitry responds to the detection of a possible system coherency failure condition by dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner.

US Patent:

62928600, Sep 18, 2001

Filed:

Dec 16, 1997

Appl. No.:

8/991697

Inventors:

Arthur F. Cochcroft - West Columbia SC
Edward A. McDonald - Baton Rouge LA
Byron L. Reams - Lexington SC
Harry W. Scrivener - Columbia SC
Bobby W. Batchler - Columbia SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1300

US Classification:

710108

Abstract:

A deadlock-avoidance system for a computer. In a multi-bus, multi-processor computer, one processor may request a lock on a bus, to execute a locked cycle, thereby blocking all other processors, and other agents, from access to the bus. In addition, a conflicting agent may, in effect, lock a resource which is needed by the processor to complete the cycle for which the lock was requested. These two locks can create a deadlock situation which stalls the computer: the processor and the conflicting agent have each locked a resource needed by the other. Under the invention, when a locked cycle is requested by a processor, all other operations are suspended in the computer. Then queues standing in memory controllers are emptied. If a process requested by an agent occupies a resource, such as a bridge, required by the requested locked cycle, that resource is freed. Then the locked cycle is executed.

US Patent:

60121270, Jan 4, 2000

Filed:

Dec 12, 1997

Appl. No.:

8/989371

Inventors:

Edward A. McDonald - Baton Rouge LA
James M. Ottinger - Duluth GA
Harry W. Scrivener - Columbia SC

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711141

Abstract:

A multiprocessor computing apparatus including a plurality of processors each having a cache memory and preferably arranged in nodes on a system bus. A first cache coherency providing mechanism coupled to the processors for achieving system level cache coherency. A second cache coherency providing mechanism is also provided. When an error is detected in the first cache coherency providing mechanism, this mechanism is disabled and cache coherency is achieved by the second cache coherency providing mechanism. In a preferred embodiment, the first mechanism includes coherency directories and the second mechanism includes bus snooping.

US Patent:

20190068193, Feb 28, 2019

Filed:

Sep 26, 2018

Appl. No.:

16/142627

Inventors:

- Coppell TX, US
Harry SCRIVENER - Lawrenceville GA, US

International Classification:

H03K 19/0175
G06F 17/50
H01L 23/528
H01L 23/50

Abstract:

An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.