Harm P Hofstee

US Patent:

6335650, Jan 1, 2002

Filed:

Sep 28, 2000

Appl. No.:

09/670829

Inventors:

David William Boerstler - Round Rock TX
Harm Peter Hofstee - Austin TX
Hung Cai Ngo - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03H 1126

US Classification:

327261, 327530

Abstract:

A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.

US Patent:

6430672, Aug 6, 2002

Filed:

Jul 17, 2000

Appl. No.:

09/617829

Inventors:

Sang Hoo Dhong - Austin TX
Harm Peter Hofstee - Austin TX
Osamu Takahashi - Round Rock TX
Jan van Lunteren - Adliswil, CH

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1210

US Classification:

711220, 711 5, 711202, 711206, 711208, 711209

Abstract:

A method for performing address mapping for a memory within a computer system is disclosed. The memory is organized in multiple of memory banks, and each memory bank is identified by a respective bank number. A block address portion of a physical address is translated to a corresponding bank number and an associated internal bank address. The bank number is formed by concatenating an output from a first lookup table and an output from a second lookup table. The output from the first lookup table is obtained by a first and a second segments of the block address portion, while the output from the second lookup table is obtained by a third and a fourth segments of the block address portion. Data stored in a specific location within the memory banks can be accessed by the bank number and the associated internal bank address.

US Patent:

6502224, Dec 31, 2002

Filed:

Apr 12, 2001

Appl. No.:

09/833413

Inventors:

Sang Hoo Dhong - Austin TX
Harm Peter Hofstee - Austin TX
Stephen Douglas Posluszny - Round Rock TX
Joel Abraham Silberman - Somers NY
Osamu Takahashi - Round Rock TX
Dieter F. Wendel - Schoenaich, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 6, 716 7, 716 18

Abstract:

A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.

US Patent:

6507115, Jan 14, 2003

Filed:

Dec 14, 2000

Appl. No.:

09/736584

Inventors:

Harm Peter Hofstee - Austin TX
Robert Kevin Montoye - Austin TX
Edmund Juris Sprogis - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2348

US Classification:

257777, 257686, 257685, 257778, 361760, 438108, 438109

Abstract:

A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.

US Patent:

6541847, Apr 1, 2003

Filed:

Feb 4, 2002

Appl. No.:

10/066999

Inventors:

Harm P. Hofstee - Austin TX
Eric A. Johnson - Greene NY
Randall J. Stutzman - Vestal NY
Jamil A. Wakil - Binghamton NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2302

US Classification:

257686, 257723, 257724, 257777

Abstract:

An electrical structure or package, and associated method of formation. A plurality of logic chips is coupled electrically to a memory chip either through conductive members (e. g. , solder balls) that interface with the memory chip and each logic chip, or through a sequential logic-to-memory electrically conductive path that includes: a first conductive member electrically coupled to a logic chip; an electrically conductive via path through a circuitized substrate; and a second conductive member electrically coupled to the memory chip. The logic chips are electrically coupled to the substrate either directly through an interfacing solder interconnection from the logic chip to the substrate, or indirectly through the memory chip such that the memory chip is electrically coupled to the substrate by an interfacing solder interconnect. The electrical structure may be plugged into a socket of a backplane of a circuit card.

US Patent:

6587941, Jul 1, 2003

Filed:

Feb 4, 2000

Appl. No.:

09/498089

Inventors:

Brian King Flacks - Georgetown TX
Harm Peter Hofstee - Austin TX
Osamu Takahashi - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 930

US Classification:

712218, 712228, 712244, 714 15, 714 16

Abstract:

A pipelined processor and method are disclosed including an improved history file unit. The pipelined processor processes a plurality of instructions in order. A register file is included which includes a different read port coupled to each register field in an instruction buffer for reading data from the register file. A history file unit is included and is coupled to each of the read ports of the register file for receiving a copy of all data read from the register file.

US Patent:

6598153, Jul 22, 2003

Filed:

Dec 10, 1999

Appl. No.:

09/458407

Inventors:

Brian King Flachs - Georgetown TX
Harm Peter Hofstee - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 938

US Classification:

712234, 712215, 712219

Abstract:

A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.

US Patent:

6600959, Jul 29, 2003

Filed:

Feb 4, 2000

Appl. No.:

09/498934

Inventors:

Paula Kristine Coulman - Austin TX
Sang Hoo Dhong - Austin TX
Brian King Flachs - Georgetown TX
Harm Peter Hofstee - Austin TX
Jaehong Park - Seongnam, KR
Stephen Douglas Posluszny - Round Rock TX
Joel Abraham Silberman - Somers NY
Osamu Takahashi - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05B 1918

US Classification:

700 7, 326 39, 326 41, 326 47

Abstract:

A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.