Fatha S Khalsa

US Patent:

20110057302, Mar 10, 2011

Filed:

Apr 9, 2010

Appl. No.:

12/757466

Inventors:

James Raymond Spehar - Chandler AZ, US
Christian Paquet - Cupertino CA, US
Wayne A. Nunn - Hidden Valley Lake CA, US
Dominicus M. Roozeboom - San Jose CA, US
Joseph E. Schulze - Chandler AZ, US
Fatha Khalsa - San Jose CA, US

Assignee:

NXP B.V - Eindhoven

International Classification:

H01L 23/498
H01L 23/538
G06F 17/50

US Classification:

257693, 257723, 703 14, 257784, 257E23169, 257E2306, 716106

Abstract:

A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.

US Patent:

20130268909, Oct 10, 2013

Filed:

Jun 5, 2013

Appl. No.:

13/910921

Inventors:

- Eindhoven, NL
Christian PAQUET - Cupertino CA, US
Wayne A. NUNN - Hidden Valley Lake CA, US
Dominicus Marinus ROOZEBOOM - San Jose CA, US
Joseph SCHULZE - Chandler AZ, US
Fatha KHALSA - San Jose CA, US

International Classification:

G06F 17/50

US Classification:

716132

Abstract:

A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.