Farinaz Koushanfar

US Patent:

8054098, Nov 8, 2011

Filed:

Jan 4, 2011

Appl. No.:

12/984275

Inventors:

Farinaz Koushanfar - Houston TX, US
Miodrag Potkonjak - Los Angeles CA, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

H03K 19/00

US Classification:

326 8, 326 47

Abstract:

Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

US Patent:

8176448, May 8, 2012

Filed:

Jun 5, 2009

Appl. No.:

12/479665

Inventors:

Farinaz Koushanfar - Houston TX, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

G06F 17/50

US Classification:

716102, 716101, 716104

Abstract:

Techniques are generally described for designing an integrated circuit (IC). In various embodiments, the techniques include designing, at a functional specification level, N-variants of a particular circuit. The various embodiments may then implement the designed N-variants as hardware in the IC. Additional variants and embodiments may also be disclosed.

US Patent:

8365131, Jan 29, 2013

Filed:

Jan 11, 2010

Appl. No.:

12/685114

Inventors:

Farinaz Koushanfar - Houston TX, US
Miodrag Potkonjak - Los Angeles CA, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

G06F 17/50

US Classification:

716132, 716122, 716123, 716133

Abstract:

Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

US Patent:

8370787, Feb 5, 2013

Filed:

Aug 25, 2009

Appl. No.:

12/547382

Inventors:

Farinaz Koushanfar - Houston TX, US
Miodrag Potkonjak - Los Angeles CA, US

Assignee:

Empire Technology Development LLC - Wilmington DE

International Classification:

G06F 11/22
G06F 17/50

US Classification:

716136, 716106, 716110, 716111, 716112, 714715, 714724, 714725, 714729, 726 25, 703 4, 703 14, 703 15

Abstract:

Methods, apparatuses and articles for testing security of a mapping function—such as a Physically Unclonable Function (PUF)—of an integrated circuit (IC) are disclosed. In various embodiments, one or more tests may be performed. In various embodiments, the tests may include a predictability test, a collision test, a sensitivity test, a reverse-engineering test and an emulation test. In various embodiments, a test may determine a metric to indicate a level of security or vulnerability. In various embodiments, a test may include characterizing one or more delay elements and/or path segments of the mapping function. Other embodiments may be described and claimed.

US Patent:

8387071, Feb 26, 2013

Filed:

Aug 28, 2009

Appl. No.:

12/550132

Inventors:

Miodrag Potkonjak - Los Angeles CA, US
Farinaz Koushanfar - Houston TX, US

Assignee:

Empire Technology Development, LLC - Wilmington DE

International Classification:

G06F 9/44

US Classification:

719318, 326 8

Abstract:

Techniques are generally described for transitioning a Finite State Machine (FSM) of an integrated circuit from a first state to a second state or a replicated variant of the second state in lieu of the second state, and out of the replicated variant of the second state, using a robust physically unclonable function (PUF), an event generator and a control block of the IC. In various embodiments, the techniques leverage on manufacturing variability of the IC. In various embodiments, the techniques are employed to control activation or deactivation of the IC. Other embodiments may be disclosed and claimed.

US Patent:

8417754, Apr 9, 2013

Filed:

May 11, 2009

Appl. No.:

12/463984

Inventors:

Miodrag Potkonjak - Los Angeles CA, US
Farinaz Koushanfar - Houston TX, US

Assignee:

Empire Technology Development, LLC - Wilmington DE

International Classification:

G06F 7/38
G06F 7/10

US Classification:

708446, 708323, 708160, 708250, 708270

Abstract:

Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

US Patent:

8443034, May 14, 2013

Filed:

Jun 5, 2009

Appl. No.:

12/479584

Inventors:

Farinaz Koushanfar - Houston TX, US
Miodrag Potkonjak - Los Angeles CA, US

Assignee:

Empire Technology Development, LLC - Wilmington DE

International Classification:

G01F 31/31835
H03H 11/40

US Classification:

708800, 708446, 708323

Abstract:

Techniques are generally described for selecting input vectors that reduce or minimize leakage current for a plurality of integrated circuits (ICs) with the same design, but that differ due to manufacturing variability. In various embodiments, the techniques include determining at least one starting input vector that reduces leakage current in a respective one of N instances of the ICs, and selecting from the determined at least one starting input vector of each respective one of the N instances, a set R of representative input vectors. Some of the embodiments then use each of the representative input vectors in the set R to determine at least a particular input vector to apply to input terminals of an IC in the plurality of ICs to reduce or minimize leakage current in the IC. Additional variants and embodiments may also be disclosed.

US Patent:

8620982, Dec 31, 2013

Filed:

Apr 2, 2013

Appl. No.:

13/855421

Inventors:

Farinaz Koushanfar - Houston TX, US

Assignee:

Empire Technology Development, LLC - Wilmington DE

International Classification:

G06F 7/38
G06F 7/00

US Classification:

708446, 708208, 708490, 708802

Abstract:

Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.