IBM
Manager, HSS Design & Verification
IBM 2011 - 2013
Engineering Manager - Analog Physical Design
IBM Sep 2006 - Aug 2011
Functional Logic Verification Engineer
Education:
University of Vermont 2008 - 2011
MBA, Business Administration
Universität Karlsruhe (TH) 2010 - 2010
Rochester Institute of Technology 2005 - 2006
Master of Science (M.S.), Computer Engineering
Rochester Institute of Technology 2001 - 2006
Bachelor of Science (B.S.), Computer Engineering
Languages:
Igbo
Awards:
Beta Gamma Sgima Honor society for Business Administration
Senior Manager And Principal Verification Engineer
Idt - Integrated Device Technology, Inc. Aug 2013 - May 2017
Manager and Engineer, Functional Logic Verification Engineering
Idt - Integrated Device Technology, Inc. Aug 2013 - May 2017
Senior Manager and Principal Verification Engineer
Ibm Jan 2013 - Aug 2013
Manager, Hss Design and Verification
Ibm 2011 - 2013
Engineering Manager - Analog Physical Design
Ibm Sep 2006 - Aug 2011
Functional Logic Verification Engineer
Education:
University of Vermont 2008 - 2011
Master of Business Administration, Masters, Business Administration, Business
Karlsruhe Institute of Technology (Kit) 2010 - 2010
Rochester Institute of Technology 2001 - 2006
Bachelors, Bachelor of Science, Computer Engineering
Rochester Institute of Technology 2005 - 2006
Master of Science, Masters, Computer Engineering
Skills:
People Managegment Managing Globally Staffed Projects Employee Coaching Functional Verification Systemverilog Programming Verification Technical Leadership Fpga Testing Analog Systems Engineering Semiconductors Java Physical Design Unix Perl Verilog Very Large Scale Integration Debugging Application Specific Integrated Circuits
Kenneth J. Goodnow - Essex Junction VT, US Suzanne Granato - Essex Junction VT, US Eze Kamanu - Essex Junction VT, US Todd E. Leonard - Williston VT, US Ramnath Ravindran - Burlington VT, US Kyle E. Schneider - Bristol VT, US Peter A. Twombly - Shelburne VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 3/00 G06F 3/01 G06F 3/023 G06F 3/03
US Classification:
702117, 702120, 702121, 702123
Abstract:
An integrated circuit (IC) including a warranty and enforcement system, and a related design structure and HDL design structure are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded.
Warranty Monitoring And Enforcement For Integrated Circuit
Kenneth J. Goodnow - Essex Junction VT, US Suzanne Granato - Essex Junction VT, US Eze Kamanu - Essex Junction VT, US Todd E. Leonard - Williston VT, US Ramnath Ravindran - Burlington VT, US Kyle E. Schneider - Bristol VT, US Peter A. Twombly - Shelburne VT, US
International Classification:
G06Q 99/00
US Classification:
705 1
Abstract:
An integrated circuit (IC) including a warranty and enforcement system and a method are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded.
Adam J. Courchesne - Essex Junction VT, US Johnathan P. Ebbers - Essex Junction VT, US Kenneth J. Goodnow - Essex Junction VT, US Suzanne Granato - Essex Junction VT, US Eze Kamanu - Essex Junction VT, US Kyle E. Schneider - Essex Junction VT, US Peter A. Twombly - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716100
Abstract:
A method configures a plurality of circuit elements for execution of an application in a first configuration. The method monitors the execution of the application on the plurality of circuit elements to produce monitoring information, using a computerized device, and stores the monitoring information in a storage structure. The method selectively communicates the monitoring information to an external element separate from the computerized device. The external element transforms the first configuration into a second configuration based on the monitoring information. The computerized device receives the second configuration from the external element and reconfigures the plurality of elements into the second configuration.
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