Erich Robert Klawuhn

US Patent:

6566246, May 20, 2003

Filed:

May 21, 2001

Appl. No.:

09/862539

Inventors:

Tarek Suwwan de Felipe - Mountain View CA
Michal Danek - Cupertino CA
Erich Klawuhn - San Jose CA
Alexander Dulkin - Sunnyvale CA

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 214763

US Classification:

438627, 438687

Abstract:

The present invention pertains to systems and methods for improving the deposition of conformal copper seed layers in integrated circuit metalization. The invention involves controlling the morphology of the barrier layer deposited underneath the copper seed layer. The barrier layer can be composed of TaN and Ta, or TaN alone. It can also be composed of TiN or TiNSi. The process conditions of the barrier layer deposition are carried out in a manner that results in a highly or completely amorphous crystalline structure. Such a barrier layer allows for conformal deposition of the copper seed layer on top of the barrier layer that is less susceptible to agglomeration.

US Patent:

6541371, Apr 1, 2003

Filed:

Jan 26, 2000

Appl. No.:

09/491853

Inventors:

Kaihan A. Ashtiani - Sunnyvale CA
Maximilian A. Biberger - Palo Alto CA
Erich R. Klawuhn - San Jose CA
Kwok Fai Lai - Palo Alto CA
Karl B. Levy - Los Altos CA
J. Patrick Rymer - Livermore CA

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 214763

US Classification:

438627, 438629, 438653, 438656

Abstract:

A method of depositing thin films comprising tantalum, tantalum nitride, and copper for barrier films and seed layers within high aspect ratio openings used for copper interconnects. The barrier films and seed layers are deposited at extremely low temperature conditions wherein the wafer stage temperature of the sputter source is chilled to about -70Â C. to about 0Â C. Most preferably, the present invention is practiced using a hollow cathode magnetron. The resulting tantalum and/or tantalum nitride barrier films and copper seed layers are superior in surface smoothness, grain size and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.

US Patent:

6541374, Apr 1, 2003

Filed:

Sep 26, 2001

Appl. No.:

09/965471

Inventors:

Tarek Suwwan de Felipe - Mountain View CA
Michal Danek - Cupertino CA
Erich Klawuhn - San Jose CA
Ronald A. Powell - San Carlos CA

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 214763

US Classification:

438648, 438653, 438656, 438687

Abstract:

The present invention pertains to methods for forming diffusion barrier layers in the context of integrated circuit fabrication. Methods of the invention allow selective deposition of a metal-nitride barrier layer material on a partially fabricated integrated circuit having exposed conductor and dielectric regions and conversion of the metal-nitride barrier material into an effective diffusion barrier layer having low via resistance. In a preferred method using TiN, differential morphology in a single barrier layer deposition is achieved by controlling CVD process conditions. It is believed that the absolute amount of TiN deposited on the conductor is not reduced, but the morphology of is changed so that there is little or no increase in the via resistance after barrier formation. The invention also pertains to novel integrated circuit structures resulting from application of the described methods.

US Patent:

6554914, Apr 29, 2003

Filed:

Feb 2, 2001

Appl. No.:

09/776704

Inventors:

Robert T. Rozbicki - San Jose CA
Ronald Allan Powell - San Carlos CA
Erich Klawuhn - San Jose CA
Michal Danek - Sunnyvale CA
Karl B. Levy - Los Altos CA
Jonathan David Reid - Sherwood OR
Mukul Khosla - San Jose CA
Eliot K. Broadbent - Beaverton OR

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C23C 824

US Classification:

148238, 148282

Abstract:

The present invention pertains to systems and methods for passivating the copper seed layer deposited in Damascene integrated circuit manufacturing. More specifically, the invention pertains to systems and methods for depositing the copper seed layer by physical vapor deposition, while passivating the copper during or immediately after the deposition in order to prevent excessive oxidation of the copper. The invention is applicable to dual Damascene processing.

US Patent:

6607977, Aug 19, 2003

Filed:

Sep 26, 2001

Appl. No.:

09/965472

Inventors:

Robert Rozbicki - San Jose CA
Michal Danek - Cupertino CA
Erich Klawuhn - San Jose CA

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 214763

US Classification:

438627, 438597, 438622, 438625, 438672, 438687, 438643, 438653

Abstract:

The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

US Patent:

6642146, Nov 4, 2003

Filed:

Apr 10, 2002

Appl. No.:

10/121949

Inventors:

Robert Rozbicki - San Francisco CA
Michal Danek - Cupertino CA
Erich Klawuhn - San Jose CA

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 2144

US Classification:

438687, 438622, 438624, 438625, 438627, 438628, 438629, 438637, 438638, 438644, 438648, 438654, 438656, 438666, 438668, 438672, 438675, 438678, 438685

Abstract:

The present invention pertains to methods for depositing a metal seed layer on a wafer substrate having a plurality of recessed features. Methods of the invention include at least two operations. A first portion of a seed layer is deposited such that metal ions impinge on the wafer substrate substantially perpendicular to the wafer substrate work surface. The first portion is characterized by heavy bottom coverage in the recessed features and minimal overhang on the apertures of the recessed features. A second portion of the metal seed layer is deposited with simultaneous re-sputter of at least part of the first portion that covers the bottom of the features. During re-sputter, part of the seed material on the bottom is redistributed to the sidewalls of the features. Seed layers of the invention have minimal overhang and excellent step coverage.

US Patent:

6905959, Jun 14, 2005

Filed:

Dec 31, 2002

Appl. No.:

10/335464

Inventors:

Kaihan A. Ashtiani - Sunnyvale CA, US
Maximilian A. Biberger - Palo Alto CA, US
Erich R. Klawuhn - San Jose CA, US
Kwok Fai Lai - Palo Alto CA, US
Karl B. Levy - Los Altos CA, US
J. Patrick Rymer - Livermore CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L021/4763

US Classification:

438648, 438643, 438627, 438653, 438656, 438685

Abstract:

A method of depositing thin films comprising tantalum, tantalum nitride, and copper for barrier films and seed layers within high aspect ratio openings used for copper interconnects. The barrier films and seed layers are deposited at extremely low temperature conditions wherein the wafer stage temperature of the sputter source is chilled to about −70 C. to about 0 C. Most preferably, the present invention is practiced using a hollow cathode magnetron. The resulting tantalum and/or tantalum nitride barrier films and copper seed layers are superior in surface smoothness, grain size and uniformity such that subsequent filling of the high aspect ratio opening is substantially void-free.

US Patent:

7510634, Mar 31, 2009

Filed:

Nov 10, 2006

Appl. No.:

11/558693

Inventors:

Erich R. Klawuhn - Los Altos CA, US
Robert Rozbicki - San Francisco CA, US
Girish A. Dixit - San Jose CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C23C 14/35

US Classification:

20429803, 20429816, 20429817, 20429818, 20429823, 20429829, 20419217

Abstract:

Disclosed are apparatus and method embodiments for achieving etch and/or deposition selectivity in vias and trenches of a semiconductor wafer. That is, deposition coverage in the bottom of each via of a semiconductor wafer differs from the coverage in the bottom of each trench of such wafer. The selectivity may be configured so as to result in punch through in each via without damaging the dielectric material at the bottom of each trench or the like. In this configuration, the coverage amount deposited in each trench is greater than the coverage amount deposited in each via.