Edward F Jeng

US Patent:

6449748, Sep 10, 2002

Filed:

Aug 9, 1999

Appl. No.:

09/370856

Inventors:

Edward Jewjing Jeng - Fremont CA
Lamberto Beleno - Milpitas CA
Steve Kehchien Hsuing - Sunnyvale CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 4, 257 48

Abstract:

Provided is a non-destructive method of detecting die crack problems in an integrated circuit. The method provides for testing for die crack problems in all chips and in many production chips without adding any extra circuitry or pads. In a preferred embodiment, the method takes advantage of an existing NAND gate tree structure at the perimeter of many conventional dies, although the invention is also applicable to other logic gate structures that may exist or may be formed at the perimeter of dies. The invention recognizes that this NAND gate tree structure may be used in order to identify and localize die cracks in finished chips, thereby providing a faster, more accurate and nondestructive way to test for die cracks in production chips. A typical NAND gate tree structure has the form of a cascade inverter chain. Since one end of the first NAND gate is tied to V , the output of each gate will alternate between low and high.

US Patent:

62925229, Sep 18, 2001

Filed:

Nov 13, 1997

Appl. No.:

8/969401

Inventors:

Edward Jewjing Jeng - Fremont CA
Benedict Man-Fui Lok - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03D 324

US Classification:

375376

Abstract:

A phase-locked loop cell includes a voltage-controlled oscillator adapted to produce an oscillating signal. A test input to the phase-locked loop is adapted to cause the voltage-controlled oscillator to generate a test oscillating signal. A frequency decoder is coupled to the output of the voltage controlled oscillator and is adapted to provide a voltage related to the frequency of the test oscillating signal.

US Patent:

60971991, Aug 1, 2000

Filed:

Jan 22, 1998

Appl. No.:

9/010938

Inventors:

Edward Jewjing Jeng - Fremont CA
Son Truong Nguyen - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3102

US Classification:

324755

Abstract:

Provided is a universal decoder test board (UDTB) capable of performing the package interface and pin scrambling functions of a conventional DUT board with a variety of different package designs. The UDTB is designed such that it is capable of interfacing with a variety of different tester interface boards, each tester interface board associated with its own hardware manufacturer tester. The UDTB significantly reduces the time and expense invested in test boards required for testing semiconductor device packages for a variety of different manufacturers'platforms by allowing a given package type to be tested with a plurality of testers on the same UDTB.