Douglas Robert Chisholm

US Patent:

58025464, Sep 1, 1998

Filed:

Dec 13, 1995

Appl. No.:

8/573221

Inventors:

Douglas Roderick Chisholm - Delray Beach FL
Gary Hoch - Coral Springs FL
Timothy Vincent Lee - Raleigh NC
Andrew Boyce McNeill - Apex NC
Ed Wachtel - New York NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1200

US Classification:

711100

Abstract:

An information handling system transfers data blocks between a host processing side having a host processing unit and a host memory and a local processing side having a local processing unit and a local memory. The host memory includes a status queue memory portion having a plurality of status queue images each image storing a status information relating to a corresponding data transfer. The status information relating to data block transfers are posted on the host processing side. The host processing unit, upon system initialization, sets up a status queue register set within the local processing side defining status queue parameters including the location of the status queue memory portion within the host memory and pointer values pointing to where status queue images are to be stored and from where they are to be retrieved.

US Patent:

52768147, Jan 4, 1994

Filed:

May 10, 1989

Appl. No.:

7/351181

Inventors:

Donall G. Bourke - Boca Raton FL
Douglas R. Chisholm - Delray Beach FL
Gregory D. Float - Vestal NY
Richard A. Kelley - Coral Springs FL
Roy Y. Liu - borh of Vestal NY
Carl A. Malmquist - borh of Vestal NY
John M. Nelson - Apalachin NY
Charles B. Perkins - Endicott NY
Richard L. Place - Vestal NY
Hartmut R. Schwermer - Stuttgart, DE
John D. Wilson - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1338
G06F 1310

US Classification:

395275

Abstract:

In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.

US Patent:

54559162, Oct 3, 1995

Filed:

Jan 10, 1995

Appl. No.:

8/371041

Inventors:

Donall G. Bourke - Boca Raton FL
Douglas R. Chisholm - Delray Beach FL
Gregory D. Float - Vestal NY
Richard A. Kelley - Coral Springs FL
Roy Y. Liu - Vestal NY
Carl A. Malmquist - Vestal NY
John M. Nelson - Apalachin NY
Charles B. Perkins - Endicott NY
Richard L. Place - Vestal NY
Hartmut R. Schwermer - Stuttgart, DE
John D. Wilson - Endwell NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1340
G06F 1342
G06F 1338

US Classification:

395285

Abstract:

In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

US Patent:

57940690, Aug 11, 1998

Filed:

Dec 13, 1995

Appl. No.:

8/572265

Inventors:

Douglas Roderick Chisholm - Delray Beach FL
Gary Hoch - Coral Springs FL
Timothy Vincent Lee - Raleigh NC
Andrew Boyce McNeill - Apex NC
Ed Wachtel - New York NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1300
G06F 1314

US Classification:

395822

Abstract:

An information handling system transfers data blocks between a host processing side having a CPU and a host memory and a local processing side having a local processing unit and a local memory. The local memory includes a DCB queue memory portion having a plurality of DCB images each image defining host and local addresses of a corresponding data transfer. The DCB images also store a default status condition representing the most likely condition of a data transfer which in the preferred embodiment is a no error condition. A data transfer status detector determines whether the default status condition is true or false. If true, the default status information relating to a corresponding data block transfer is posted on the host processing side without local processing unit intervention.

US Patent:

50034650, Mar 26, 1991

Filed:

Jun 27, 1988

Appl. No.:

7/212292

Inventors:

Douglas R. Chisholm - Delray Beach FL
Robert G. Iseminger - Binghamton NY
Richard A. Kelley - Coral Springs FL
Wan L. Leung - Coral Springs FL
James T. Moyer - Endwell NY
Mark C. Snedaker - Vestal NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1300

US Classification:

364200

Abstract:

In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of "storage latency" that occur after a DMA storage operation has been initiated by one IOP.

US Patent:

43731813, Feb 8, 1983

Filed:

Jul 30, 1980

Appl. No.:

6/173586

Inventors:

Douglas R. Chisholm - Delray Beach FL
Hobart L. Kurtz - Boca Raton FL

International Classification:

G06F 930

US Classification:

364200

Abstract:

A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appearance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.

US Patent:

59408669, Aug 17, 1999

Filed:

Dec 13, 1995

Appl. No.:

8/572234

Inventors:

Douglas Roderick Chisholm - Delray Beach FL
Gary Hoch - Coral Springs FL
Timothy Vincent Lee - Raleigh NC
Andrew Boyce McNeill - Apex NC
Ed Wachtel - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1312

US Classification:

711170

Abstract:

An information handling system transfers command blocks between a host processing side having a host processing unit and a host memory, and a local processing side having a local processing unit and a local memory. The local memory includes a command address queue portion for queuing local command address images containing the local addresses of the command blocks. A command block transfer controller is responsive to the local command address images for storing the transferred command block into a corresponding portion of the local memory.

US Patent:

59681438, Oct 19, 1999

Filed:

Dec 13, 1995

Appl. No.:

8/572235

Inventors:

Douglas Roderick Chisholm - Delray Beach FL
Gary Hoch - Coral Springs FL
Timothy Vincent Lee - Raleigh NC
Andrew Boyce McNeill - Apex NC
Ed Wachtel - New York NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1312

US Classification:

710 23

Abstract:

An information handling system transfers command blocks between a host processing side having a host processing unit and a host memory and a local processing side having a local processing unit and a local memory. The command blocks are transferred from the host processing side to the local processing side by storing the host address of the command block in a local side register set. Upon storing the host address a transfer signal is given to a command block transfer controller to start a command block transfer without the local processor unit intervention.