Dirk Fuhrmann

US Patent:

7136295, Nov 14, 2006

Filed:

May 6, 2005

Appl. No.:

11/123841

Inventors:

Dirk Fuhrmann - Essex Junction VT, US
Reidar Lindstedt - München, DE

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 5/06

US Classification:

365 63, 365149, 365150

Abstract:

A semiconductor arrangement on a semiconductor chip includes a number of lines of a first type that extend outwardly from an inner region toward an outer region of the semiconductor chip. A number of lines of a second type are arranged around the inner region of the semiconductor chip. The lines of the second type are bit lines when the lines of the first type are word lines and the lines of the second type are word lines when the lines of the first type are bit lines. A number of individual element arrays are arranged along the lines of the first type and lines of the second type. The individual element arrays include memory cells.

US Patent:

7197679, Mar 27, 2007

Filed:

Apr 1, 2005

Appl. No.:

11/095670

Inventors:

Dirk Fuhrmann - Essex Junction VT, US
Reidar Lindstedt - München, DE

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 29/00

US Classification:

714719, 714742

Abstract:

An integrated semiconductor memory operates in synchronization with a clock signal in a normal operating state and is switched from the normal operating state to a test operating state by applying a combination of control signals. During a first test cycle, selection transistors for memory cells are turned on by asynchronously actuating the semiconductor memory using a state change in a control signal. In a second test cycle, the memory content of at least one of the previously activated memory cells is read by synchronously actuating the semiconductor memory using a second signal combination of control signals. By shifting the timing of a signal edge which prompts the state change in the first test cycle close to the time at which the second signal combination is applied in the second test cycle, it is possible to test short reading times which are within one period of the clock signal.

US Patent:

7313033, Dec 25, 2007

Filed:

Sep 28, 2005

Appl. No.:

11/236933

Inventors:

Dirk Fuhrmann - Apex NC, US
Jan Zieleman - Cary NC, US
Norbert Rehm - Apex NC, US
Rob Perry - Cary NC, US
Rath Ung - Apex NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 7/00

US Classification:

36518909, 36518911

Abstract:

A random access memory including first memory cells, second memory cells, a first voltage source, and a second voltage source. The first voltage source is configured to control the first memory cells. The second voltage source is configured to control the second memory cells. Also, the first voltage source is configured to be trimmed independently of the second voltage source to provide a first voltage that reduces leakage from the first memory cells and the second voltage source is configured to be trimmed independently of the first voltage source to provide a second voltage that reduces leakage from the second memory cells.

US Patent:

7313044, Dec 25, 2007

Filed:

Feb 4, 2005

Appl. No.:

11/050428

Inventors:

Dirk Fuhrmann - Essex Junction VT, US
Reidar Lindstedt - München, DE

Assignee:

Infineon Technologies, AG - Munich

International Classification:

G11C 7/04

US Classification:

365211, 365212, 365226

Abstract:

An integrated semiconductor memory device includes a temperature sensor circuit to generate a temperature-dependent control signal, a reference circuit to generate a temperature-independent reference signal, a comparator circuit and a voltage generator circuit. The comparator circuit generates a first level or second level of an activation signal in a manner dependent on the comparison of the control signal and the reference signal which are both fed to it on an input side. The voltage generator circuit generates a first control signal or a second control signal in a manner dependent on the level of the activation signal. The integrated semiconductor memory enables the generation of two control signals for a selection transistor of a memory cell in a manner dependent on whether the temperature sensor circuit detects a temperature in a first temperature range or in a second temperature range.

US Patent:

7330387, Feb 12, 2008

Filed:

Nov 7, 2005

Appl. No.:

11/267572

Inventors:

Reidar Lindstedt - Ottobrunn, DE
Dirk Fuhrmann - Apex NC, US

Assignee:

Infineon Technologies, AG - Neubiberg

International Classification:

G11C 7/00
G11C 8/00

US Classification:

365205, 365207, 365208, 36518912, 365226

Abstract:

An integrated semiconductor memory device includes a sense amplifier that is connected to a first bit line via a first output connection and is connected to a second bit line via a second output connection. A memory cell to store a first or a second memory state is connected to the first bit line. When writing/reading the first memory state, the sense amplifier produces a negative voltage at the first output connection and a positive voltage at the second output connection, and when writing/reading the second memory state, it produces the positive voltage at the first output connection and the negative voltage at the second output connection. The production of a negative voltage results in one of the two bit lines being charged approximately to a ground potential during a read or write access.

US Patent:

7443740, Oct 28, 2008

Filed:

Feb 16, 2006

Appl. No.:

11/355200

Inventors:

Dirk Fuhrmann - Apex NC, US
Matthias Skalitz - Unterschleiβheim, DE

Assignee:

Infineon Technologies AG - Neubiberg

International Classification:

G11C 7/00

US Classification:

36518911, 365201, 3652331

Abstract:

An integrated semiconductor memory includes a clock generator circuit for generating an internal clock signal that exhibits a certain phase angle with respect to an external clock signal. The phase angle is dependent on a value of the supply voltage of the clock generator circuit. The supply voltage is provided by a controllable voltage generator that includes a controllable resistor. During the production process, the supply voltage generated can be picked up at a contact pad. The value of the controllable resistor is changed in each memory chip by an automatic production machine until the supply voltage generated matches a target value. The controllable voltage generator can be adjusted individually for each memory chip via fuse elements so that the target value of the supply voltage is achieved with high accuracy for each memory chip.

US Patent:

7457177, Nov 25, 2008

Filed:

Dec 21, 2005

Appl. No.:

11/314605

Inventors:

Rob Perry - Cary NC, US
Norbert Rehm - Apex NC, US
Jan Zieleman - Cary NC, US
Rath Ung - Apex NC, US
Dirk Fuhrmann - Apex NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 29/00

US Classification:

365201, 36518907

Abstract:

A random access memory including an array of memory cells configured to store memory cell data, a first circuit, and a second circuit. The first circuit is configured to compare test data and memory cell data to obtain comparison results. The second circuit is configured to compress the comparison results and store the compressed comparison results.

US Patent:

7362632, Apr 22, 2008

Filed:

Jan 17, 2006

Appl. No.:

11/333037

Inventors:

Norbert Rehm - Apex NC, US
Rath Ung - Apex NC, US
Rob Perry - Cary NC, US
Jan Zieleman - Cary NC, US
Dirk Fuhrmann - Apex NC, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G11C 29/00
G01R 31/02

US Classification:

365201, 324754, 714718

Abstract:

Embodiments of the invention generally provide methods and systems for increasing the level of parallelism in testing memory devices. A set of test signals provided by a memory tester may be shared by two or more devices under test. A chip selector may be used to select at least one or all the devices sharing a given set of test signals. By sharing test signals between multiple devices, the level of parallel testing may be increased without increasing the pin count and complexity of memory testers and probe cards.