Dennis C Abts

Address:

401 Pinnacle Way UNIT 306, Eau Claire, WI 54701

VIN:

2HNYD28827H538888

Make:

ACURA

Model:

MDX

Year:

2007

Address:

S8930 Stonebrook Dr, Eleva, WI 54738

VIN:

JTHBE262X75013414

Make:

LEXUS

Model:

IS 350

Year:

2007

US Patent:

7830905, Nov 9, 2010

Filed:

Apr 21, 2008

Appl. No.:

12/107036

Inventors:

Steven L. Scott - Chippewa Falls WI, US
Gregory Hubbard - Chippewa Falls WI, US
Kelly Marquardt - Chippewa Falls WI, US
Roger A. Bethard - Chippewa Falls WI, US
Dennis C. Abts - Eleva WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

H04L 12/56

US Classification:

370419, 370386

Abstract:

A system and method for speculative forwarding of packets received by a router, wherein each packet includes phits and wherein one or more phits include a cyclic redundancy code (CRC). A packet is received and phits of the packet are forwarded to router logic. A cyclic redundancy code for the packet is calculated and compared to the packet's cyclic redundancy code. An error is generated if the cyclic redundancy codes don't match. If the cyclic redundancy codes don't match, a phit of the packet is modified to reflect the error, the CRC is corrected and the corrected CRC is forwarded to the router logic along with the phit reflecting the CRC error. At the router logic, a check is made to see if the packet is still within the router logic. If the packet is still within the router logic and there was a CRC error, the packet is discarded. If, however, the packet is no longer within the router logic and there was a CRC error, the packet is modified so that the next router discards the packet.

US Patent:

7843929, Nov 30, 2010

Filed:

Apr 21, 2008

Appl. No.:

12/107016

Inventors:

Steven L. Scott - Chippewa Falls WI, US
Gregory Hubbard - Chippewa Falls WI, US
Dennis C. Abts - Chippewa Falls WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

H04L 12/56

US Classification:

370392, 370395

Abstract:

A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.

US Patent:

7852836, Dec 14, 2010

Filed:

Oct 31, 2007

Appl. No.:

11/932413

Inventors:

Steven L. Scott - Chippewa Falls WI, US
Dennis C. Abts - Chippewa Falls WI, US
Gregory Hubbard - Chippewa Falls WI, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370388, 370412, 370413, 370414, 710317

Abstract:

A system and method for routing packets from one node to another node in a system having a plurality of nodes connected by a network. A node router is provided in each node, wherein the node router includes a plurality of network ports, including a first and a second network port, wherein each network port includes a communications channel for communicating with one of the other network nodes, a plurality of virtual channel input buffers and a plurality of virtual channel staging buffers, wherein each of the virtual channel staging buffers receives data from one of the plurality of input buffers.

US Patent:

7864792, Jan 4, 2011

Filed:

Apr 21, 2008

Appl. No.:

12/107019

Inventors:

Steven L. Scott - Chippewa Falls WI, US
Dennis C. Abts - Eleva WI, US
William J. Dally - Stanford CA, US

Assignee:

Cray, Inc. - Seattle WA

International Classification:

H04L 12/56

US Classification:

370419, 370392

Abstract:

In a system having a N output ports, wherein N is an integer greater than one, a method of distributing packets across the plurality of output ports. A packet having two or more fields is received and a first number is computed as a function of one or more of the plurality of fields. A second number is computed that is modulo base N of the first number and an output port is selected as a function of the second number.

US Patent:

8065573, Nov 22, 2011

Filed:

Nov 19, 2008

Appl. No.:

12/274044

Inventors:

Dennis C. Abts - Eleva WI, US
Gerald A Schwoerer - Chippwa Falls WI, US
Van L. Snyder - Blaine MN, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

G11C 29/00

US Classification:

714723, 714704, 714711, 365200

Abstract:

Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.

US Patent:

8095759, Jan 10, 2012

Filed:

May 29, 2009

Appl. No.:

12/474556

Inventors:

Dennis C. Abts - Eleva WI, US
Steven L. Scott - Chippewa Falls WI, US
Aaron F. Godfrey - Eagan MN, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

G06F 12/14

US Classification:

711163, 711E12091, 712 30, 712 E9002

Abstract:

A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising a part of one or more of the nodes is operable to prevent a write from an unauthorized processor from writing to the local memory.

US Patent:

8184626, May 22, 2012

Filed:

Jan 12, 2009

Appl. No.:

12/352443

Inventors:

Steven L. Scott - Chippewa Falls WI, US
Dennis C. Abts - Eleva WI, US
William J. Dally - Stanford CA, US

Assignee:

Cray Inc. - Seattle WA
The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

H04L 12/50

US Classification:

370362, 370364, 370539, 700 2, 700 4, 710 51, 710 52

Abstract:

A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input ports, output ports, row busses, columns channels and a plurality of subswitches arranged in a n x p matrix. Each row bus receives data from one of the plurality of input ports and distributes the data to two or more of the plurality of subswitches. Each column distributes data from one or more subswitches to one or more output ports. Each row bus includes a route selector, wherein the route selector includes a routing table which selects an output port for each packet and which routes the packet through one of the row busses to the selected output port.

US Patent:

8239704, Aug 7, 2012

Filed:

Jun 12, 2009

Appl. No.:

12/483886

Inventors:

Steven L. Scott - Chippewa Falls WI, US
Dennis C. Abts - Eleva WI, US
Aaron F. Godfrey - Eagan MN, US

Assignee:

Cray Inc. - Seattle WA

International Classification:

G06F 1/04

US Classification:

713600, 713500

Abstract:

In some embodiments, the present invention relates to a method of maintaining a global clock within a multiprocessor system having a plurality of nodes that are connected in a network via links. A virtual spanning tree is mapped onto the network and the nodes and the links are configured such that each node is in a parent-child relationship with one or more other nodes in the virtual spanning tree. A global clock is generated in a root of the virtual spanning tree and global clock signals are communicated down the virtual spanning tree to each of the nodes.