David R Madsen

Author:

David P Madsen

ISBN #:

0130985147

Author:

David B. Madsen

ISBN #:

0874804655

Author:

David B. Madsen

ISBN #:

0874803314

Author:

David B. Madsen

ISBN #:

0874807867

Author:

David B. Madsen

ISBN #:

0874806054

Author:

David B. Madsen

ISBN #:

0874806119

Author:

David B. Madsen

ISBN #:

0874808413

Author:

David P. Madsen

ISBN #:

0131149822

US Patent:

20100197567, Aug 5, 2010

Filed:

Oct 16, 2009

Appl. No.:

12/580487

Inventors:

Andres Villu MARICQ - Salt Lake City UT, US
Stori JENSEN - Salt Lake City UT, US
Craig WALKER - Salt Lake City UT, US
David MADSEN - West Valley City UT, US
Baldomero OLIVERA - Salt Lake City UT, US
Michael ELLISON - Thornton CO, US

Assignee:

UNIVERSITY OF UTAH RESEARCH FOUNDATION - Salt Lake City UT

International Classification:

A61K 38/14
A61K 38/17
C07K 9/00
C07K 14/435
C07H 21/04
A61P 25/28
A61P 25/00
G01N 33/68

US Classification:

514 8, 514 12, 530322, 530324, 530350, 536 235, 436 86

Abstract:

The invention relates to peptides (termed propeller peptides herein) and related peptides (termed peptides of the G12.2 family herein), about 60 to about 90 residues in length, which are naturally available in minute amounts in the venom of the cone snails or analogous to the naturally available peptides, and which blocks the desensitization of AMPA-type ionotropic glutamate receptors (AMPARs).

US Patent:

20190294554, Sep 26, 2019

Filed:

Mar 26, 2018

Appl. No.:

15/935203

Inventors:

- Cambridge, GB
Kim Richard SCHUTTENBERG - Gilbert AZ, US
David MADSEN - Chandler AZ, US
Lalit BANSAL - Scottsdale AZ, US
Sriram SAMYNATHAN - Chandler AZ, US

International Classification:

G06F 12/109

Abstract:

An apparatus and method are provided for handling access requests. The apparatus has processing circuitry for processing a plurality of program threads to perform data processing operations on data, where the operations identify the data using virtual addresses, and the virtual addresses are mapped to physical addresses within a memory system. The cache storage has a plurality of cache entries to store data, an aliasing condition existing when multiple virtual addresses map to the same physical address, and allocation of data into the cache storage being constrained to prevent multiple cache entries of the cache storage simultaneously storing data for the same physical address. Cache access circuitry is then responsive to an access request specifying a virtual address, to utilise a cache index at least partially determined from the specified virtual address to identify at least one cache entry within the cache storage, and to detect whether a hit is present within the at least one cache entry by comparing a physical address portion associated with that cache entry with a tag portion of the physical address corresponding to the specified virtual address. Remap handling circuitry is then arranged whilst a first program thread is in the process of performing an exclusive operation using a first virtual address to identify a specified physical address whose data is stored in the cache storage, to detect a remap condition when a second program thread issues a second program thread access request of at least one type that specifies a second virtual address that exhibits the aliasing condition with the first virtual address. In the presence of the remap condition, the remap handling circuitry remaps the cache index at least partially determined from the second virtual address, so that the remapped cache index as then used by the cache access circuitry matches the cache index at least partially determined from the first virtual address. This provides an effective mechanism for avoiding potential live-lock scenarios that can otherwise arise.