David Bormann - Sunnyvale CA Leslie E. Cline - Sunnyvale CA Frank Hart - Apex NC
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 126
US Classification:
713323, 713300, 713320
Abstract:
A peripheral device having a circuit to detect the power management state of a central processor, a first interface to receive data, and a second interface to couple the peripheral device to the central processor. The peripheral device prevents data transfers that would cause the central processor to change from a second power management state to a first power management state if the central processor is in the second power management state.
David S. Bormann - Sunnyvale CA Kirk W. Skeba - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1314
US Classification:
710110, 710305, 370351
Abstract:
Transmitting data on a serial data transmission path to reduce latency including reading only enough of a device address of a serial data word to determine if the serial data word is addressed to a first device having an address, wherein the serial data word is transmitted across a first link of a first serial data transmission path to the first device and passing the serial data word across a second link of the first serial data transmission path to a second device if the serial data word is not addressed to the first device.
Method And Apparatus To Directly Access A Peripheral Device When Central Processor Operations Are Suspended
David Bormann - Sunnyvale CA Leslie E. Cline - Sunnyvale CA Frank Hart - Apex NC Rudi Rughoonundon - Santa Clara CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 126
US Classification:
713324, 713300, 713323, 710 36, 710 38
Abstract:
A method and apparatus for facilitating direct access to computer resources by a peripheral device while the computers CPU is in a sleeping state. A peripheral device having a circuit to detect the power management state of a central processor, a first interface to couple the device to the central processor if the circuit detects the first power management state, and a second interface to couple the device to a peripheral device if the circuit detects the second power management state.
Method And Apparatus Facilitating Direct Access To A Parallel Ata Device By An Autonomous Subsystem
David S. Bormann - Sunnyvale CA, US Chao-Hsin Chi - San Jose CA, US Frank P. Hart - Apex NC, US Dong Tieu - Union City CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/28
US Classification:
713340, 713323, 710 14
Abstract:
A method and apparatus for facilitating direct access to a parallel Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).
Method And Apparatus Facilitating Direct Access To A Serial Ata Device By An Autonomous Subsystem
David S. Bormann - Sunnyvale CA, US Chao-Hsin Chi - San Jose CA, US Frank P. Hart - Apex NC, US Dong Tieu - Union City CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/28
US Classification:
713340, 713323, 710 14
Abstract:
A method and apparatus for facilitating direct access to a serial Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).
Method And Apparatus To Permit A Peripheral Device To Become The Default System Bus Master
David Bormann - Sunnyvale CA, US Leslie Cline - Sunnyvale CA, US Frank Hart - Apex NC, US Siripong Sritanyaratana - Union City CA, US
International Classification:
G06F013/00
US Classification:
710/110000
Abstract:
A method and apparatus for facilitating direct access to computer resources by a peripheral device while the computer's CPU is in a sleeping state. Said method and apparatus comprising a configurable link to enable a peripheral device to become the default system bus master when the main CPU is in a sleep state.
Speculative Memory Command Preparation For Low Latency
Speculative memory commands are prepared for reduced latency. A system memory read request is sent for preparing a main memory read command and for performing a cache lookup. The main memory read command is prepared independent from the performance of the cache lookup.
Identification Of Wireless Devices Based On Signal Characteristics
David Cheung - Santa Clara CA, US David Bormann - San Jose CA, US Scott Ettinger - Mountain View CA, US
International Classification:
H04Q 7/00
US Classification:
370328
Abstract:
A method and apparatus for identification of wireless devices based on signal characteristics. An embodiment of a method includes receiving a signal from a wireless device and generating a spectrogram of the received signal. The method further provides for identifying one or more regions of the spectrogram and processing the spectrogram to determine time, bandwidth, and density characteristics of the identified regions.