David W Boerstler

US Patent:

6335650, Jan 1, 2002

Filed:

Sep 28, 2000

Appl. No.:

09/670829

Inventors:

David William Boerstler - Round Rock TX
Harm Peter Hofstee - Austin TX
Hung Cai Ngo - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03H 1126

US Classification:

327261, 327530

Abstract:

A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.

US Patent:

6353369, Mar 5, 2002

Filed:

Nov 30, 2000

Appl. No.:

09/726285

Inventors:

David William Boerstler - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03B 524

US Classification:

331 57, 331177 R, 331179

Abstract:

A voltage controlled oscillator is provided comprising a plurality of delay elements serially connected to form a ring and each element within the plurality of elements includes an input and output. The voltage controlled oscillator also includes a set of control elements where each control element within the set of control elements has an input connected to an input of a delay element within the set of delay elements and an output connected to an output of a different delay element within the plurality of delay elements. A control voltage is selectively applied to control elements within the set of control elements to vary the oscillating frequency and phase distribution in proportion to the control voltage. In addition, the voltage controlled oscillator includes a selection unit connected to the set of control elements. The selection unit selectively enables, disables, and regulates groups of control elements to alter the gain and the range of frequency adjustment attainable by the control voltage or the voltage controlled oscillator.

US Patent:

6384649, May 7, 2002

Filed:

Feb 22, 2001

Appl. No.:

09/791150

Inventors:

David William Boerstler - Round Rock TX
Sani Richard Nassif - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03L 706

US Classification:

327156, 327161

Abstract:

An apparatus and method for measuring clock skew in a digital system. A phase detector generates an error signal proportional to a phase difference between signals applied to first and second phase detector inputs. A controlled oscillator produces an output signal having a frequency that is proportional to the filtered error signal. In accordance with the method of the present invention, the feedback path from the output of the controlled oscillator to the second input of the phase detector is opened. A sequence of pairs of mutually delayed signals are applied to the first and second phase detector inputs to obtain a range of delay reference values. A pair of skew measurement node signals from within the digital system are applied to the first and second phase detector inputs to obtain a skew response. The skew response is evaluated with respect to the range of delay reference values to obtain a skew result.

US Patent:

6441667, Aug 27, 2002

Filed:

Mar 29, 2001

Appl. No.:

09/820460

Inventors:

David William Boerstler - Round Rock TX
Robert Keven Montoye - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 104

US Classification:

327295, 327159, 327150, 327162, 375376, 331DIG 2

Abstract:

The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

US Patent:

6480049, Nov 12, 2002

Filed:

Nov 28, 2001

Appl. No.:

09/996043

Inventors:

David William Boerstler - Round Rock TX
Robert Keven Montoye - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 300

US Classification:

327299, 327254, 327244, 327159, 331DIG 2, 375376, 3652235

Abstract:

The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate voltage which controls the frequency of the MVCO and to generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

US Patent:

6483888, Nov 19, 2002

Filed:

Oct 11, 2001

Appl. No.:

09/974987

Inventors:

David W. Boerstler - Round Rock TX
Gary D. Carpenter - Pflugerville TX
Hung C. Ngo - Austin TX
Kevin J. Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 2100

US Classification:

377 47, 327115, 327117, 327159, 327415

Abstract:

A clock divider circuit receives a first clock signal and frequency divides the first clock signal to generate a second clock signal. The first and second clocks are inputs to multiplexer (MUX) that selects one of the clocks as the MUX output based on the state of a MUX control signal. The MUX output is combined with a latched Freeze clock signal in an AND gate to generate a clock output signal. The state of Bypass logic signal determines which clock signal is selected as the clock output signal. The Bypass logic signal is received in a latch circuit which latches the Bypass logic signal in two series latches one latch latching on the positive edge and one on the negative edge of the MUX output. The output of the second latch is latched in a third latch on when a NOR logic gate signals the first and second clock are concurrently at a logic zero assuring that the MUX output is changed only when both clocks are low. The clock output signal is gated with the latched Freeze clock signal in the AND logic gate.

US Patent:

6501304, Dec 31, 2002

Filed:

Oct 11, 2001

Appl. No.:

09/974990

Inventors:

David W. Boerstler - Round Rock TX
Gary D. Carpenter - Pflugerville TX
Hung C. Ngo - Austin TX
Kevin J. Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1700

US Classification:

327 99, 327 34, 327407

Abstract:

A glitch-free clock selector selects between asynchronous clock signals. In one embodiment a select signal has two logic states corresponding to the two clock signals. A clock output signal is gated with a latched compare signal which compares a new select signal state to a stored current select signal state. A multiplexer (MUX) selects between the two clock signals in response to a select latch output signal. If the new and current select signals do not compare the clock output signal is forced to a logic zero by the output of a compare latch which latches the compare signal when the MUX output (present selected clock signal) goes to a logic zero. While the present clock signal is held low, the MUX switches to the new clock signal. The new clock signal (MUX output) latches the new select state as the current select state causing the new and current select signal to compare. The new clock signal (MUX output) latches the compare signal and again enables the clock output signal when the new clock signal transitions from a one to a zero.

US Patent:

6501313, Dec 31, 2002

Filed:

Dec 27, 2000

Appl. No.:

09/749335

Inventors:

David William Boerstler - Round Rock TX
Daniel Mark Dreps - Georgetown TX
Byron Lee Krauter - Austin TX
Hung Cai Ngo - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3017

US Classification:

327175, 327276, 327278, 327534

Abstract:

A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer. Alternatively, the invention may be implemented in an analog fashion, such as by applying an analog signal to the body contact, wherein the analog signal is generated using an asymmetric charge-pump and filter connected to the clock signal.