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Darryl S Jessie

age ~58

from Star, ID

Also known as:
  • Darryl Sheldon Jessie
  • Darell S Jessie
  • Darryl Jeesie
  • Jessie S Darryl

Darryl Jessie Phones & Addresses

  • Star, ID
  • 16629 Gill Loop, San Diego, CA 92127 • 8583678818
  • 11293 Miro Cir, San Diego, CA 92131
  • 9974 Kika Ct, San Diego, CA 92129
  • Escondido, CA

Us Patents

  • Variable Inductor For Integrated Circuit And Printed Circuit Board

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  • US Patent:
    7460001, Dec 2, 2008
  • Filed:
    Sep 25, 2003
  • Appl. No.:
    10/672904
  • Inventors:
    Darryl Jessie - San Diego CA, US
  • Assignee:
    QUALCOMM Incorporated - San Diego CA
  • International Classification:
    H01F 5/00
  • US Classification:
    336200
  • Abstract:
    A variable inductor can be formed on an integrated circuit with a primary conductor, a secondary conductor, and a switch. The primary conductor implements an inductor and may be formed in various patterns (e. g. , a spiral). The secondary conductor forms a loop in proximity to (e. g. , on the outside of) the primary conductor. The switch couples in series with the secondary conductor and opens or closes the loop. The inductance of the inductor is varied by closing and opening the loop with the switch. A current source may also be coupled in series with the secondary conductor and used to control the current flow in the secondary conductor to either increase or decrease the inductance. Multiple loops may be formed to change the inductance in more than two discrete steps. The variable inductor may be used for various applications such as filters, VCOs, and impedance matching networks.
  • Integrated Circuit With Low-Loss Primary Conductor Strapped By Lossy Secondary Conductor

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  • US Patent:
    20030202331, Oct 30, 2003
  • Filed:
    Jul 9, 2002
  • Appl. No.:
    10/192476
  • Inventors:
    Darryl Jessie - San Diego CA, US
    Charles Persico - Rancho Santa Fe CA, US
  • International Classification:
    H05K001/18
  • US Classification:
    361/764000
  • Abstract:
    Techniques for “strapping” a primary conductor with a secondary conductor in an integrated circuit (IC). The IC includes a number of circuit elements interconnected by a secondary conductor through a number of vias disposed at a number of locations for coupling the circuit elements as an alternative to a primary conductor. The primary conductor is typically formed with a low loss metal (e.g., copper or copper alloy), and the secondary conductor is typically formed with a lossy metal (e.g., aluminum or aluminum alloy) relative to the low loss metal. The secondary conductor is strapped to the primary conductor by the vias, which may be disposed only at both ends or along the entire length of the secondary conductor. The secondary conductor is formed using design guidelines such that it provides the required electrical connectivity when the primary conductor is not present but minimally interferes with the RF performance of the primary conductor.
  • Antenna Tuner

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  • US Patent:
    20220368359, Nov 17, 2022
  • Filed:
    May 17, 2021
  • Appl. No.:
    17/322294
  • Inventors:
    - San Diego CA, US
    Darryl Sheldon Jessie - San Diego CA, US
  • International Classification:
    H04B 1/04
    H04B 1/16
    H04B 1/10
    H01Q 23/00
  • Abstract:
    An apparatus is disclosed for implementing an antenna tuner. In an example aspect, the apparatus includes a substrate, an antenna disposed on or in the substrate, a radio-frequency integrated circuit disposed on the substrate, and an antenna tuner. The radio-frequency integrated circuit includes an amplification circuit. The antenna tuner is coupled between the antenna and the amplification circuit. The antenna tuner includes an inductive component disposed on or in the substrate and a capacitive component implemented within the radio-frequency integrated circuit.
  • Discrete Antenna Module With Via Wall Structure

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  • US Patent:
    20220190485, Jun 16, 2022
  • Filed:
    Dec 11, 2020
  • Appl. No.:
    17/119638
  • Inventors:
    - San Diego CA, US
    Mohammad Ali TASSOUDJI - San Diego CA, US
    Jeongil Jay KIM - San Diego CA, US
    Darryl Sheldon JESSIE - San Diego CA, US
    Kevin Hsi-Huai WANG - San Diego CA, US
  • International Classification:
    H01Q 21/06
    H01Q 5/307
    H01Q 1/48
    H01Q 19/10
    H01Q 1/24
  • Abstract:
    Techniques are provided for improving the performance of a multi-band antenna in a wireless device. An example wireless device includes at least one radio frequency integrated circuit, and at least one patch antenna operably coupled to the at least one radio frequency integrated circuit, including a first patch operably coupled to the at least one radio frequency integrated circuit, a ground plane disposed below the first patch, and a plurality of via wall structures disposed around the first patch, wherein each of the plurality of via wall structures is electrically coupled to the ground plane.
  • Electromagnetic (Em) Field Rotation For Interconnection Between Chip And Circuit Board

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  • US Patent:
    20220192006, Jun 16, 2022
  • Filed:
    Dec 15, 2020
  • Appl. No.:
    17/122820
  • Inventors:
    - San Diego CA, US
    Darryl Sheldon JESSIE - San Diego CA, US
  • Assignee:
    QUALCOMM Incorporated - San Diego CA
  • International Classification:
    H05K 1/02
    H05K 1/11
  • Abstract:
    Certain aspects of the present disclosure generally relate to a circuit board with ground vias offset from associated ground bumps. One example circuit board generally includes a first signal connection terminal configured to connect a signal line of the circuit board to an integrated circuit (IC); a ground plane having a first ground connection terminal disposed adjacent to the first signal connection terminal, the first ground connection terminal being configured to provide a ground connection between the ground plane and the IC; and a first ground via associated with and disposed adjacent to the first ground connection terminal and coupled to the ground plane, wherein, from an overhead view of the circuit board, the first ground via is located at a position that is offset from a first axis on which the first signal connection terminal and the first ground connection terminal are disposed.
  • Systems For Shielding Bent Signal Lines

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  • US Patent:
    20210410274, Dec 30, 2021
  • Filed:
    Nov 20, 2020
  • Appl. No.:
    17/100121
  • Inventors:
    - San Diego CA, US
    Suhyung Hwang - Rancho Mission Viejo CA, US
    Mina Iskander - San Diego CA, US
    Rajneesh Kumar - San Diego CA, US
    Darryl Sheldon Jessie - San Diego CA, US
  • International Classification:
    H05K 1/02
    H01Q 21/06
    H01Q 1/48
    H01Q 1/22
  • Abstract:
    Systems for shielding bent signal lines provide ways to couple different antenna arrays for radio frequency (RF) integrated circuits (ICs) (RFICs) associated therewith where the antenna arrays are oriented in different directions. Because the antenna arrays are oriented in different directions, the antenna structures containing the antennas may be arranged in different planes, and signal lines extending therebetween may include a bend. To prevent electromagnetic interference (EMI) or electromagnetic crosstalk (EMC) from negatively impacting signals on the signal lines, the signal lines may be shielded. The shields may further include vias connecting the mesh ground planes and positioned exteriorly of the signal lines. The density of the vias may be varied to provide a desired rigidity in planes containing the antenna arrays while providing a desired flexibility at a desired bending location in the signal lines to help bending process accuracy.
  • Multi-Core Broadband Pcb Antenna

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  • US Patent:
    20210351488, Nov 11, 2021
  • Filed:
    May 11, 2020
  • Appl. No.:
    16/871822
  • Inventors:
    - San Diego CA, US
    Suhyung HWANG - Rancho Mission Viejo CA, US
    Jaehyun YEON - San Diego CA, US
    Taesik YANG - San Diego CA, US
    Jeongil Jay KIM - San Diego CA, US
    Darryl Sheldon JESSIE - San Diego CA, US
    Mohammad Ali TASSOUDJI - San Diego CA, US
  • International Classification:
    H01Q 1/12
    H05K 1/02
    H05K 3/46
    H05K 3/00
  • Abstract:
    A multi-core broadband printed circuit board (PCB) antenna and methods for fabricating such an antenna are provided. One example antenna implemented with a multi-core PCB generally includes a first core structure, a second core structure disposed above the first core structure, and one or more metal layers disposed above the second core structure or below the first core structure. The first core structure includes a first core layer, a first metal layer disposed below the first core layer, and a second metal layer disposed above the first core layer. The second core structure includes a second core layer, a third metal layer disposed below the second core layer, and a fourth metal layer disposed above the second core layer. The first core layer and the second core layer may have different thicknesses.
  • Device Comprising Multi-Directional Antennas In Substrates Coupled Through Flexible Interconnects

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  • US Patent:
    20210280959, Sep 9, 2021
  • Filed:
    Mar 5, 2020
  • Appl. No.:
    16/810621
  • Inventors:
    - San Diego CA, US
    Rajneesh KUMAR - San Diego CA, US
    Suhyung HWANG - Rancho Mission Viejo CA, US
    Jaehyun YEON - San Diego CA, US
    Mohammad Ali TASSOUDJI - San Diego CA, US
    Darryl Sheldon JESSIE - San Diego CA, US
    Ameya GALINDE - San Diego CA, US
  • International Classification:
    H01Q 1/22
    H01Q 1/52
    H01Q 1/36
    H05K 1/18
    H05K 9/00
    H01L 23/31
    H01L 23/538
    H01L 23/66
    H01L 23/552
    H01L 21/56
  • Abstract:
    A device that includes a first substrate comprising a first antenna, an integrated device coupled to the first substrate, an encapsulation layer located over the first substrate and the integrated device, a second substrate comprising a second antenna, and a flexible connection coupled to the first substrate and the second substrate. The device includes a shield formed over a surface of the encapsulation layer and a surface of the first substrate. The shield includes an electromagnetic interference (EMI) shield.
Name / Title
Company / Classification
Phones & Addresses
Darryl Jessie
President & Chief Executive Officer
Raum Energy
Wind Energy Systems
3718A Millar Ave, Saskatoon, SK S7P 0B1
3066510586, 3066510605
Darryl Jessie
President & Chief Executive Officer
Raum Energy
Wind Energy Systems
3066510586, 3066510605

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