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Clifford E Kimmery

age ~72

from Clearwater, FL

Also known as:
  • Clifford E Kimmer
Phone and address:
1623 Jacob Ct, Clearwater, FL 33756
7274475291

Clifford Kimmery Phones & Addresses

  • 1623 Jacob Ct, Clearwater, FL 33756 • 7274475291
  • 2045 Sunset Grove Ln, Clearwater, FL 33765
  • Clearwater Beach, FL
  • 20355 E Silverhill Ave, Robertsdale, AL 36567
  • Loxley, AL
  • Largo, FL

Us Patents

  • Common Protocol And Routing Scheme For Space Data Processing Networks

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  • US Patent:
    7720099, May 18, 2010
  • Filed:
    Aug 13, 2007
  • Appl. No.:
    11/838013
  • Inventors:
    David R. Bueno - Pinellas Park FL, US
    Clifford E. Kimmery - Clearwater FL, US
  • Assignee:
    Honeywell International Inc. - Morristown NJ
  • International Classification:
    H04J 3/16
  • US Classification:
    370469, 370464, 370465
  • Abstract:
    A method of communicatively coupling network elements supporting multiple network protocol types comprises receiving input having multiple network protocol types from an upper-level of the protocol stack at an endpoint-flexible-interface layer in a network endpoint, mapping the input between the upper-level of a protocol stack and a common-lower-level in the protocol stack at the endpoint-flexible-interface layer, and implementing the common-lower-level protocol layer to interface the multiple network protocol types to the physical layer, so that at least two endpoints of a network are communicatively coupled.
  • Virtual Network Architecture For Space Data Processing

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  • US Patent:
    8031633, Oct 4, 2011
  • Filed:
    Aug 13, 2007
  • Appl. No.:
    11/838023
  • Inventors:
    David R. Bueno - Pinellas Park FL, US
    Clifford E. Kimmery - Clearwater FL, US
  • Assignee:
    Honeywell International Inc. - Morristown NJ
  • International Classification:
    H04L 12/24
  • US Classification:
    370254, 370401, 709226
  • Abstract:
    An adaptable virtual network system comprises a plurality of network elements and a plurality of virtual links. Each network element is communicatively coupled to at least one other network element via at least one physical link. At least one physical link comprises at least two virtual links. The adaptable virtual network system supports at least two virtual networks, each virtual network comprising at least one virtual link communicatively coupling at least two network elements.
  • Methods And Systems For Refresh And Error Scrubbing Of Dynamic Memory Devices

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  • US Patent:
    20070022244, Jan 25, 2007
  • Filed:
    Jul 25, 2005
  • Appl. No.:
    11/188312
  • Inventors:
    Clifford Kimmery - Clearwater FL, US
  • Assignee:
    HONEYWELL INTERNATIONAL INC. - MORRISTOWN NJ
  • International Classification:
    G06F 13/28
  • US Classification:
    711106000
  • Abstract:
    Methods and systems for refresh and error scrubbing of dynamic memory devices is provided. A method for maintaining the integrity of data stored in dynamic memory devices comprises determining a refresh-scrub-access-period time interval for a dynamic memory device having a plurality of memory elements, based on a refresh rate requirement for the dynamic memory device and an error scrub rate requirement; and performing an error-scrub function on each memory element of the dynamic memory device at a periodicity not exceeding the refresh-scrub-access-period time interval.
  • Global Memory For A Rapidio Network

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  • US Patent:
    20070124554, May 31, 2007
  • Filed:
    Oct 28, 2005
  • Appl. No.:
    11/261087
  • Inventors:
    Mark Allen - Clearwater FL, US
    Clifford Kimmery - Clearwater FL, US
    James Parker - Tarpon Springs FL, US
    Daniel Tabor - Belleair Beach FL, US
  • Assignee:
    Honeywell International Inc. - Morristown NJ
  • International Classification:
    G06F 12/00
  • US Classification:
    711163000
  • Abstract:
    Systems and methods for global memory for a RapidIO network are provided. In one embodiment, a method for accessing global data on a RapidIO network comprises obtaining ownership of a global memory unit (GMU) and receiving a data write packet at a GMU endpoint on a RapidIO network. The data write packet includes a source network identifier and a dataset. The method further comprises verifying whether the source network identifier matches a lock owner network identifier stored in a first register, and verifying one or both of whether one or both of a processor endpoint and a controller endpoint are permitted to alter the lock owner network identifier, and whether the source network identifier identifies a processor endpoint authorized to write data on the GMU based on a set of authorized source network identifiers stored in a second register. The method further comprises storing the dataset on the GMU.
  • Fault Tolerance In A Distributed Processing Network

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  • US Patent:
    20070186126, Aug 9, 2007
  • Filed:
    Feb 6, 2006
  • Appl. No.:
    11/348277
  • Inventors:
    Grant Smith - Tampa FL, US
    Jason Noah - Redington Shores FL, US
    Clifford Kimmery - Clearwater FL, US
  • Assignee:
    Honeywell International Inc. - Morristown NJ
  • International Classification:
    G06F 11/00
  • US Classification:
    714004000
  • Abstract:
    A distributed processing network is disclosed. The network includes at least one network switch, coupled to one or more end nodes, and adapted to simultaneously receive and route a plurality of data packets between the one or more end nodes. Within the network, the one or more end nodes are interconnected by one or more communication links adapted to provide a predetermined level of fault tolerant error detection and recovery.
  • Method To Embed Protocol For System Management Bus Implementation

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  • US Patent:
    20080059682, Mar 6, 2008
  • Filed:
    Aug 31, 2006
  • Appl. No.:
    11/469207
  • Inventors:
    Stephen Cooley - Seminole FL, US
    Clifford E. Kimmery - Clearwater FL, US
    Louis F. Villarosa - Tampa FL, US
  • Assignee:
    Honeywell International Inc. - Morristown NJ
  • International Classification:
    G06F 13/14
  • US Classification:
    710305
  • Abstract:
    A method of adapting the System Management Bus protocol to increase the number of peripheral components accessible to a control processor, the method including embedding a component address having a length of up to seven bits in a System Management Bus Block Write and completing a system transaction with the System Management Bus Block Write and a second data packet so that data is sent between the control processor and the peripheral component having the component address.
  • Alternating Fault Tolerant Reconfigurable Computing Architecture

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  • US Patent:
    20080120500, May 22, 2008
  • Filed:
    Nov 20, 2006
  • Appl. No.:
    11/561500
  • Inventors:
    Clifford E. Kimmery - Clearwater FL, US
    Grant L. Smith - Tampa FL, US
    Richard P. White - Seminole FL, US
  • Assignee:
    Honeywell International Inc. - Morristown NJ
  • International Classification:
    G06F 1/00
    G06F 9/44
  • US Classification:
    713100, 713375
  • Abstract:
    A method for reducing radiation effects in an electronic circuit is disclosed. The method involves periodically transferring operation of the electronic circuit to at least one alternate processing element of a plurality of processing elements. With the at least one alternate processing element in control, the method reconfigures one or more processing elements of the plurality of processing elements. Once the one or more processing elements are reconfigured, the method synchronizes the one or more processing elements with the at least one alternate processing element.
  • System Management Bus Port Switch

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  • US Patent:
    20080123677, May 29, 2008
  • Filed:
    Aug 31, 2006
  • Appl. No.:
    11/469176
  • Inventors:
    Stephen Cooley - Seminole FL, US
    Clifford E. Kimmery - Clearwater FL, US
    Louis F. Villarosa - Tampa FL, US
  • Assignee:
    Honeywell International Inc. - Morristown NJ
  • International Classification:
    H04L 12/56
    H04J 3/16
  • US Classification:
    370419, 370466
  • Abstract:
    A method of sending data packets between a control processor and a plurality of peripheral components comprising retrieving information embedded in a command data packet formatted in a first protocol at a switch adapted to function as an alternate bus, forming a reformatted data packet at the switch, and transferring the reformatted data packet from the switch. The reformatted data packet is formatted according to a second protocol, and includes the retrieved information.
Name / Title
Company / Classification
Phones & Addresses
Clifford E. Kimmery
President, Director
Programmable Logic User Group
Vocational School School/Educational Services
10380 131 St, Largo, FL 33774
7275957878

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