Chi-Hing Choi

US Patent:

6507081, Jan 14, 2003

Filed:

Mar 9, 2001

Appl. No.:

09/803232

Inventors:

Preston Smith - Portland OR
Chi-hing Choi - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257410, 257774, 257775

Abstract:

A structure to enable damascene copper semiconductor fabrication is disclosed. There is a silicon nitride film for providing a diffusion barrier for Cu as well as an etch stop for the duel damascene process. Directly above the silicon nitride film is a silicon oxynitride film. The silicon oxynitride film is graded, to form a gradual change in composition of nitrogen and oxygen within the film. Directly above the silicon oxynitride film is silicon oxide. The silicon oxide serves as an insulator for metal lines. Preferably, the film stack of silicon nitride, silicon oxynitride and silicon oxide is all formed in sequence, within the same plasma-processing chamber, by modifying the composition of film-forming gases for forming each film.

US Patent:

6642141, Nov 4, 2003

Filed:

Mar 12, 2001

Appl. No.:

09/804608

Inventors:

Preston Smith - Portland OR
Chi-hing Choi - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438637, 438638, 438624, 438761, 438786, 438907

Abstract:

A structure to enable damascene copper semiconductor fabrication is disclosed. There is a silicon nitride film for providing a diffusion barrier for Cu as well as an etch stop for the duel damascene process. Directly above the silicon nitride film is a silicon oxynitride film. The silicon oxynitride film is graded, to form a gradual change in composition of nitrogen and oxygen within the film. Directly above the silicon oxynitride film is silicon oxide. The silicon oxide serves as an insulator for metal lines. Preferably, the film stack of silicon nitride, silicon oxynitride and silicon oxide is all formed in sequence, within the same plasma-processing chamber, by modifying the composition of film-forming gases for forming each film.

US Patent:

20030209805, Nov 13, 2003

Filed:

Mar 24, 2003

Appl. No.:

10/396659

Inventors:

Chi-Hing Choi - Portland OR, US
John Bumgarner - Tempe AZ, US
Todd Wilke - West Vancouver, CA
Melton Bost - Hillsboro OR, US

International Classification:

H01L021/50
H01L023/48
H01L029/40

US Classification:

257/758000, 257/645000, 257/646000, 257/651000, 438/118000, 438/622000, 257/776000, 438/280000

Abstract:

The present invention is a dielectric film and its method of fabrication. The dielectric film of the present invention includes silicon oxygen fluorine and nitrogen wherein the interlayer dielectric comprises between 0.01-0.1 atomic percent nitrogen.

US Patent:

62552333, Jul 3, 2001

Filed:

Dec 30, 1998

Appl. No.:

9/223197

Inventors:

Preston Smith - Portland OR
Chi-hing Choi - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2131

US Classification:

438786

Abstract:

A structure to enable damascene copper semiconductor fabrication is disclosed. There is a silicon nitride film for providing a diffusion barrier for Cu as well as an etch stop for the duel damascene process. Directly above the silicon nitride film is a silicon oxynitride film. The silicon oxynitride film is graded, to form a gradual change in composition of nitrogen and oxygen within the film. Directly above the silicon oxynitride film is silicon oxide. The silicon oxide serves as an insulator for metal lines. Preferably, the film stack of silicon nitride, silicon oxynitride and silicon oxide is all formed in sequence, within the same plasma-processing chamber, by modifying the composition of film-forming gases for forming each film.

US Patent:

20220416032, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/358436

Inventors:

- Santa Clara CA, US
Chi-Hing Choi - Portland OR, US
Gilbert Dewey - Beaverton OR, US
Harold Kennel - Portland OR, US
Omair Saadat - Portland OR, US
Jitendra Kumar Jha - Hillsboro OR, US
Adedapo Oni - North Plains OR, US
Anand Murthy - Portland OR, US
Tahir Ghani - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/417
H01L 27/088
H01L 29/161
H01L 21/8234
H01L 21/28
H01L 21/768

Abstract:

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

US Patent:

20220416050, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/359327

Inventors:

- Santa Clara CA, US
Cory BOMBERGER - Portland OR, US
Gilbert DEWEY - Beaverton OR, US
Anand S. MURTHY - Portland OR, US
Mauro KOBRINSKY - Portland OR, US
Rushabh SHAH - Hillsboro OR, US
Chi-Hing CHOI - Portland OR, US
Harold W. KENNEL - Portland OR, US
Omair SAADAT - Beaverton OR, US
Adedapo A. ONI - North Plains OR, US
Tahir GHANI - Portland OR, US

International Classification:

H01L 29/45
H01L 29/08
H01L 29/161
H01L 29/78
H01L 29/06
H01L 29/423
H01L 29/786

Abstract:

Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

US Patent:

20230101725, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/485167

Inventors:

- Santa Clara CA, US
Mauro J. KOBRINSKY - Portland OR, US
Gilbert DEWEY - Beaverton OR, US
Chi-hing CHOI - Portland OR, US
Harold W. Kennel - Portland OR, US
Brian J. KRIST - Hillsboro OR, US
Ashkar ALIYARUKUNJU - Portland OR, US
Cory BOMBERGER - Portland OR, US
Rushabh SHAH - Hillsboro OR, US
Rishabh MEHANDRU - Portland OR, US
Stephen M. CEA - Hillsboro OR, US
Chanaka MUNASINGHE - Portland OR, US
Anand S. MURTHY - Portland OR, US
Tahir GHANI - Portland OR, US

International Classification:

H01L 29/423
H01L 29/06
H01L 29/786

Abstract:

Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise germanium and boron, and a protective layer comprises silicon, and germanium that at least partially covers the epitaxial source or drain structures. A conductive contact comprising titanium silicide is on the epitaxial source or drain structures.