Charles D F Cohn

US Patent:

6465882, Oct 15, 2002

Filed:

Jul 21, 2000

Appl. No.:

09/620939

Inventors:

Charles Cohn - Wayne NJ

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 2352

US Classification:

257691, 257697

Abstract:

An integrated circuit package such as a BGA package for use with an integrated circuit chip. The integrated circuit package has substrate with a cavity that exposes a lower conductive level in the package so that connections between the integrated circuit chip and the lower conductive level may be formed to reduce the through holes formed in the substrate. As a result, additional signal line interconnections may be included in the substrate circuit package and/or the size of the integrated circuit chip may be decreased. Each of these may be implemented for enhanced electrical performance. The multiple wire bonding tiers in the substrate may also provide greater wire separation that eases wire bonding and subsequent encapsulation processes.

US Patent:

6509642, Jan 21, 2003

Filed:

Jul 28, 2000

Appl. No.:

09/628067

Inventors:

Charles Cohn - Wayne NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2334

US Classification:

257712, 257778

Abstract:

An integrated circuit package where the integrated circuit chip is mounted on a conductive slug and electrically coupled to the slug. Besides acting as a heat spreader, the conductive slug may also function as a ground plane. This reduces the need for additional conductive layers and plated through hole connections for forming connections to, for example, ground. As a result, the conductive paths in the internal ground planes are not necessarily cut off by the plated through holes used for interconnecting ground connections thus avoiding some of the electrical performance degradation suffered by prior techniques. In addition, the invention allows more signals to be added and/or the size of the integrated circuit chip to be reduced to enhance electrical performance. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.

US Patent:

6740222, May 25, 2004

Filed:

Jun 7, 2001

Appl. No.:

09/876522

Inventors:

Charles Cohn - Wayne NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

C25D 502

US Classification:

205126, 205125, 205170, 205181, 205183, 205187, 205220, 205221

Abstract:

The present invention provides a method of plating an electrical contact on an integrated circuit (IC) substrate manufactured from a rigid double-sided or multi-layered printed wiring board core with dielectric layers on both sides of the core. The method may include forming electrically connected plating layers on first and second opposing sides of a substrate and electroplating a contact layer over each of the plating layers using the plating layers. The method further includes removing a portion of the plating layers from the first and second opposing sides while leaving the plating layers under the contact layer.

US Patent:

6790760, Sep 14, 2004

Filed:

Jul 21, 2000

Appl. No.:

09/621110

Inventors:

Charles Cohn - Wayne NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 2144

US Classification:

438613, 438106, 438108, 438123, 438422, 438111, 257691, 257698, 257700, 257678

Abstract:

A method of manufacturing an integrated circuit package such as a BGA package for use with an integrated circuit chip. The integrated circuit package has a substrate formed with a cavity that exposes a lower conductive level in the package so that connections between the integrated circuit chip and the lower conductive level may be formed to reduce the through holes formed in the substrate. As a result, additional signal line interconnections may be included in the substrate circuit package and/or the size of the integrated circuit chip may be decreased. Each of these may be implemented for enhanced electrical performance. The multiple wire bonding tiers in the substrate may also provide greater wire separation that eases wire bonding and subsequent encapsulation processes.

US Patent:

7394028, Jul 1, 2008

Filed:

Feb 23, 2006

Appl. No.:

11/360200

Inventors:

Charles Cohn - Wayne NJ, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 21/44
H01R 9/09

US Classification:

174262, 257698, 257E2159, 257E23068, 438612, 438613, 438622, 174255, 174261

Abstract:

A circuit substrate for attachment to an integrated circuit chip comprises an electrical trace, a mounting pad and a dielectric layer. The mounting pad has a first surface, one or more sidewalls and a second surface. The first surface is attached to the electrical trace. The dielectric layer substantially covers the one or more sidewalls of the mounting pad and has an uppermost surface that is substantially coplanar with the second surface of the mounting pad.

US Patent:

8601683, Dec 10, 2013

Filed:

Apr 19, 2006

Appl. No.:

11/379256

Inventors:

Charles Cohn - Wayne NJ, US
Jeffrey M Klemovage - Whitehall PA, US

Assignee:

Agere Systems LLC - Wilmington DE

International Classification:

H05K 3/02
H05K 3/10

US Classification:

29846, 29829, 2281805, 228254

Abstract:

The present invention provides method of manufacture for a printed wiring board. The printed wiring board constructed according to the teachings of the present invention includes a printed wiring board dielectric layer having conductive foils located on at least two sides thereof. The printed wiring board further includes a solid core conductive material interconnecting the conductive foils.

US Patent:

20050150682, Jul 14, 2005

Filed:

Jan 12, 2004

Appl. No.:

10/755616

Inventors:

Charles Cohn - Wayne NJ, US
Jeffrey Klemovage - Whitehall PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H05K001/09
H05K001/11

US Classification:

174255000, 174262000, 174257000

Abstract:

The present invention provides a printed wiring board and a method of manufacture therefor. The printed wiring board constructed according to the teachings of the present invention includes a printed wiring board dielectric layer having conductive foils located on at least two sides thereof. The printed wiring board further includes a solid core conductive material interconnecting the conductive foils.

US Patent:

51028298, Apr 7, 1992

Filed:

Jul 22, 1991

Appl. No.:

7/733542

Inventors:

Charles Cohn - Wayne NJ

Assignee:

AT&T Bell Laboratories - Murray Hill NJ

International Classification:

H01L 2160

US Classification:

437217

Abstract:

This invention is a simple and effective process of producing a plastic pin grid array package having an encapsulated device and a heat sink forming a unitary component of a main planar body of the package. The process includes fabrication of a laminated planar main body having outer plastic sheets provided with metallizations, a metal sheet of high thermal conductivity, and plastic sheets positioned intermediate the outer plastic sheets and the metal sheet, the metal sheet having clearance holes filled with plugs of the material of the intermediate plastic sheets, a plurality of plated-through holes (PTHs) formed in the main body and terminal pins secured in the PTHs. Some of the PTHs contacting the metal sheet and some passing through the plugs in the clearance holes out of contact with the metal sheet. The device, such as an integrated circuit chip, mounted in a recessed cavity in the main body, is in contact with the metal heat-sink. In this manner heat is conducted away from the device by the heat sink and dissipated through the back of the package and those of the terminal pins which are in PTHs contacting the heat sink.