Chandra S Pawar

US Patent:

55398936, Jul 23, 1996

Filed:

Nov 16, 1993

Appl. No.:

8/153520

Inventors:

Steven A. Thompson - Coatesville PA
Chandra S. Pawar - Harleysville PA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1300

US Classification:

395449

Abstract:

The present invention provides a multi-level memory system with a multi-level memory structure and methods for allocating data among the levels of memory based on the likelihood of imminent future use. The multi-level memory structure includes a first level memory that stores the data most likely to be imminently accessed, a second level memory that stores data transferred from the first level memory when the first level memory is full, and a third level memory that stores data that is the least recently used when the second level memory is full. According to the invention, predetermined criteria and statistics are used to determine which data is likely to be imminently accessed. Once the first level memory has been full, data stored in that memory level may be rearranged based on when it is likely to be accessed. The first level memory also provides for faster access than the second level memory which in turn provides faster access then the third level memory. The data in the second level memory is maintained according to a first-in-first-out algorithm.

US Patent:

55769829, Nov 19, 1996

Filed:

Oct 17, 1994

Appl. No.:

8/323780

Inventors:

Gary C. Wu - Wayne PA
Steven H. Leibowitz - Norristown PA
Chandra S. Pawar - Harleysville PA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 700
G06F 752

US Classification:

3647151

Abstract:

Disclosed is a Significant Bit Calculator (SBC) for determining the number of significant bits or nibbles of an operand in one clock period, and for using the result in performing binary arithmetic operations, such as multiplication and division. By determining the exact size of the operand in one clock cycle, the time spent on processing leading zeros is eliminated. The SBC can be implemented with combinational logic circuitry to compute the number of significant bits or nibbles in a single clock cycle regardless of the number of leading zeros and without any firmware or counter. The time saved using the SBC is proportional to the size of the operand.

US Patent:

57040524, Dec 30, 1997

Filed:

Apr 22, 1996

Appl. No.:

8/635541

Inventors:

Gary C. Wu - Wayne PA
Chandra S. Pawar - Harleysville PA
Steven H. Leibowitz - Norristown PA
Edward J. Pullin - West Chester PA
Michael J. Hazzard - Downingtown PA
Joseph C. Duggan - Glenside PA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 752

US Classification:

395380

Abstract:

A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e. g. , multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU.