Chandra Sekhar Khandavalli

US Patent:

8587378, Nov 19, 2013

Filed:

Mar 11, 2012

Appl. No.:

13/417246

Inventors:

Chandra Khandavalli - Livermore CA, US

International Classification:

H03F 1/14

US Classification:

330292, 330149, 330109

Abstract:

An analog pre-distortion linearizer having predetermined gain and phase characteristics as a function of input RF signal power is disclosed. The linearizer comprises a core circuit comprising an input terminal configured to receive an input RF signal; an output terminal configured to provide a processed version of that signal; a transistor having a gate, a drain, and a source; and a feedback circuit, presenting an impedance at the frequency of the RF signal, connected to the transistor. The gate is connected to the input terminal and the drain is connected to the output terminal. First and second dc bias voltages applied to the gate and drain respectively cause the transistor to operate at a quiescent bias point in a saturated region of the transistor I-V plane. The quiescent bias point and the impedance are selected such that the linearizer has the predetermined gain and phase characteristics.

US Patent:

49280783, May 22, 1990

Filed:

Dec 22, 1988

Appl. No.:

7/288686

Inventors:

Chandra Khandavalli - Fremont CA

Assignee:

Avantek, Inc. - Santa Clara CA

International Classification:

H01P 518

US Classification:

333109

Abstract:

A branch line coupler is disclosed. The device is comprised of multiple ports and branch lines, every two such lines being connected in a junction point. Each branch line has a width which is narrow at each end and increases in a curvilinear manner toward the middle. By virtue of the width design, the device performs the same functions as a conventional coupler, but for much higher frequencies.

US Patent:

51326418, Jul 21, 1992

Filed:

May 1, 1991

Appl. No.:

7/694127

Inventors:

Chandra Khandavalli - Fremont CA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

H03F 368

US Classification:

330295

Abstract:

A power divider/combiner circuit is disclosed for connecting to a single port, 2N+1 multi-cell monolithic transistor chips, each chip composed of an even number of cells. A planar binary tree type transmission line structure is provided having first and second ends for connecting 2. sup. P trtansmission line ports at the first end to the single port at the second end, where N and P are each integers greater than or equal to 1, and an equal number of cells are connected to each of the 2. sup. P transmission line ports The value of P is chosen such that ##EQU1## where R is an integer greater than 1, and C is the sum total of the number of cells in the 2N+1 chips. R cells are connected to each of the 2. sup. P transmission line ports, and some cells from at least one transistor chip are connected to a transmission line port which is different from the port to which other cells from that one chip are connected.

US Patent:

20160373063, Dec 22, 2016

Filed:

Jun 18, 2015

Appl. No.:

14/743046

Inventors:

- Santa Clara CA, US
Chandra Khandavalli - Livermore CA, US

Assignee:

Eridan Communications, Inc. - Santa Clara CA

International Classification:

H03F 1/02
H03F 3/21
H03F 3/193

Abstract:

A high-power solid-state RFPA includes an output stage having a power transistor and a current enhanced driver that drives the output stage. The current enhanced driver includes an inductor and first and second transistors arranged in totem-pole-like configuration. When the first transistor is turned on and the second transistor is turned off, the inductor supplies a first charging current to the output stage, to assist in charging the input gate-source capacitor (Cgs) of the power transistor in the output stage. The first transistor further provides a second charging current that supplements the first charging current, thereby enhancing charging of the gate-source capacitor Cgs. Conversely, when the first transistor of the driver is turned off and the second transistor is turned on, the second transistor provides a discharge path through which the gate-source capacitor Cgs can discharge.