Bryan Keith Bullis

US Patent:

6519757, Feb 11, 2003

Filed:

Apr 11, 2000

Appl. No.:

09/546982

Inventors:

Bryan Keith Bullis - Apex NC
Robert Glen Gerowitz - Raleigh NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 18, 716 3

Abstract:

Descriptive statements representative of a communication level coupling the functional logic of an integrated circuit to the external environment is translated into complex functional specification language for input to hardware design programs. Plain language within the functional specifications is converted to proper design language to implement hardware described by the functional specification.

US Patent:

6876664, Apr 5, 2005

Filed:

Apr 3, 2000

Appl. No.:

09/541773

Inventors:

Bryan Keith Bullis - Apex NC, US
John Charles Goss - Wendell NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L012/56

US Classification:

370429, 370412

Abstract:

An improved asynchronous data buffer is disclosed. The data buffer comprises an entry section and a signaling circuit coupled to the entry section, the signaling circuit for signaling the data buffer to transfer a portion of a data cell from the entry section prior to the data cell being completely received by the entry section. Through the use of the data buffer in accordance with the present invention, data transfer systems are improved in two ways. Firsts by enabling data to be transferred before it is completely stored into the buffer, the latency that is typically required for data cell transfer is reduced. Second, the buffer storage space that is typically required to store a complete data cell is also reduced. This twofold improvement produces increased data transfer rates while decreasing the amount of required buffer storage space.

US Patent:

7072816, Jul 4, 2006

Filed:

Sep 30, 1999

Appl. No.:

09/409940

Inventors:

Bryan Keith Bullis - Apex NC, US
Raj Kumar Singh - Cary NC, US
Foster Beaver White - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

703 14, 703 13, 703 15, 703 22, 716 5, 716 12, 716 18

Abstract:

A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.

US Patent:

7283530, Oct 16, 2007

Filed:

Sep 26, 2002

Appl. No.:

10/255861

Inventors:

Bryan K. Bullis - Apex NC, US
Darryl J. Rumph - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56

US Classification:

370394, 3703954

Abstract:

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer and input signals from array and a clock line providing current time. The results of the search are loaded into a Winner Valid array and a Winner Location array. A final decision logic circuit parses information in the Winner Valid array and Winner Location array to generate a final Winner Valid Signal, the identity of the winning calendar and the winning location. Winning is used to define the status of the calendar in the calendar status array that is selected as a result of a search process being executed on a plurality of calendars in the calendar status array.

US Patent:

7346062, Mar 18, 2008

Filed:

Jul 10, 2003

Appl. No.:

10/617095

Inventors:

Bryan K. Bullis - Apex NC, US
Darryl J. Rumph - Cary NC, US
Michael S. Siegel - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56
H04J 3/00

US Classification:

3703954, 37039531, 370498

Abstract:

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer, and input signals from an array and a clock line providing current time. Also included is a decision block that determines which of the searches are critical and which, during peak calendar search periods, can be postponed with minimal impact to the system. The postponed searches are then conducted at a time when there is available calendar search capacity.

US Patent:

7733873, Jun 8, 2010

Filed:

Jun 27, 2007

Appl. No.:

11/769281

Inventors:

Bryan K. Bullis - Apex NC, US
Darryl J. Rumph - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56

US Classification:

3703954, 370235, 370391, 370412

Abstract:

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices, is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer and input signals from array and a clock line providing current time. The results of the search are loaded into a Winner Valid array and a Winner Location array. A final decision logic circuit parses information in the Winner Valid array and Winner Location array to generate a final Winner Valid Signal, the identity of the winning calendar and the winning location. Winning is used to define the status of the calendar in the calendar status array selected as a result of a search process being executed on a plurality of calendars in the calendar status array.

US Patent:

8139594, Mar 20, 2012

Filed:

Oct 9, 2007

Appl. No.:

11/869235

Inventors:

Bryan K. Bullis - Apex NC, US
Darryl J. Rumph - Cary NC, US
Michael S. Siegel - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/56

US Classification:

370412, 3703954, 37039541, 370414, 370236

Abstract:

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer, and input signals from an array and a clock line providing current time. Also included is a decision block that determines which of the searches are critical and which, during peak calendar search periods, can be postponed with minimal impact to the system. The postponed searches are then conducted at a time when there is available calendar search capacity.

US Patent:

56490976, Jul 15, 1997

Filed:

May 24, 1996

Appl. No.:

8/653136

Inventors:

Timothy B. Brodnax - Austin TX
Bryan K. Bullis - Woodbridge VA
Steven A. King - Herndon VA
Robert L. Schoenike - Warrenton VA
Daniel L. Stanley - Manassas VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1100

US Classification:

39518507

Abstract:

A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.