On Semiconductor
Design Center Manager - Utah Design Center
On Semiconductor Nov 2006 - Aug 2018
Senior Principal Design Engineer
Amd Jul 2000 - Nov 2006
Circuit Design Lead and Manager
National Semiconductor Jan 1997 - Jul 2000
Staff Circuit Design Engineer
Ibm Jul 1995 - Jan 1997
Custom Circuit Design Engineer
Education:
University of Utah 1985 - 1992
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Asic Cmos Mixed Signal Verilog Circuit Design Ic Rtl Design Soc Integrated Circuit Design Semiconductors Static Timing Analysis Logic Synthesis Primetime Technical Leadership Project Management Analog Vlsi Physical Design Circuit Analysis Dft Analog Circuit Design
A single transistor memory storage element has a transistor contact connected to only one of two bitlines to program a logical value for the respective bit, pulling the connected bitline away from a bitline bias voltage and creating a voltage difference between the two bitlines. A differential sense amplifier may be employed to read the programmed bit value by sensing the magnitude or polarity of the voltage difference across the two bitlines. The read only memory is thus small, suitable for embedded read only memory, but may be read quickly.
... Teresa Peake Grad Year: 1985 Tashia Peterman Grad Year: 1985 Dana Petersen Grad Year: 1985 Amy Peterson Grad Year: 1985 Jenny Goodfellow Grad Year: 1985 Blaine Prestwich Grad ...