Barry L Chin

Author:

Barry Chin

ISBN #:

0819438979

Author:

Barry Chin

ISBN #:

0933885059

Author:

Barry Chin

ISBN #:

0933885032

US Patent:

6352926, Mar 5, 2002

Filed:

Nov 10, 2000

Appl. No.:

09/709991

Inventors:

Peijun Ding - San Jose CA
Imran Hashim - San Jose CA
Barry L. Chin - Saratoga CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438687, 435734

Abstract:

We have discovered that complete copper filling of semiconductor features such as trenches and vias, without the formation of trapped voids, can be accomplished using a copper reflow process when the unfilled portion of the feature structure prior to reflow comprises a capillary within the feature, wherein the volume of the capillary represents between about 20% and about 90%, preferably between about 20% and about 75% of the original feature volume prior to filling with copper. The aspect ratio of the capillary is preferably at least 1. 5. The maximum opening dimension of the capillary is less than about 0. 8 m. The preferred substrate temperature during the reflow process includes either a soak at an individual temperature or a temperature ramp-up or ramp-down where the substrate experiences a temperature within a range from about 300Â C. to about 600Â C. , more preferably between about 300Â C.

US Patent:

6387805, May 14, 2002

Filed:

Jun 18, 1997

Appl. No.:

08/878143

Inventors:

Peijun Ding - San Jose CA
Tony Chiang - Mountain View CA
Imran Hashim - Fremont CA
Bingxi Sun - Sunnyvale CA
Barry Chin - Saratoga CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438687, 438629, 438660, 438675, 438678, 438680

Abstract:

A copper metallization structure and its method of formation in which a layer of a copper alloy, such as CuâMg or CuâAl is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

US Patent:

6399479, Jun 4, 2002

Filed:

Aug 30, 1999

Appl. No.:

09/386077

Inventors:

Fusen Chen - Cupertino CA
Zheng Xu - Foster City CA
Peijun Ding - San Jose CA
Barry Chin - Saratoga CA
Ashok Sinha - Palo Alto CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438628, 438637, 438674

Abstract:

The invention provides a method for filling a structure on a substrate comprising: depositing a barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, removing a portion of the seed layer, and electrochemically depositing a metal to fill the structure. Preferably, a portion or all of the seed layer formed on the sidewall portion of the structure is removed using a electrochemical de-plating process prior to the electroplating process.

US Patent:

6436267, Aug 20, 2002

Filed:

Aug 29, 2000

Appl. No.:

09/650108

Inventors:

Daniel A. Carl - Pleasanton CA
Barry Chin - Saratoga CA
Liang Chen - San Jose CA
Robin Cheung - Cupertino CA
Peijun Ding - San Jose CA
Yezdi Dordi - Palo Alto CA
Imran Hashim - San Jose CA
Peter Hey - Sunnyvale CA
Ashok K. Sinha - Palo Alto CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 2802

US Classification:

205186, 205123, 205157

Abstract:

One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.

US Patent:

6458251, Oct 1, 2002

Filed:

Nov 16, 1999

Appl. No.:

09/440679

Inventors:

Arvind Sundarrajan - Santa Clara CA
Darryl Angelo - Sunnyvale CA
Peijun Ding - San Jose CA
Barry Chin - Saratoga CA
Imran Hasim - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1432

US Classification:

20419212, 20419215, 20419213, 20429806, 20429807

Abstract:

A multi-step process for the deposition of a material into high aspect ratio features on a substrate surface is provided. The process involves depositing a material on the substrate at a first pressure for a first period of time and then depositing the material on the substrate at a second pressure for a second period of time. Modulation of the pressure influences the ionization and trajectory of the particles, which are ionized in a plasma environment. The method of the invention in one aspect allows for optimum deposition at the bottom of a high aspect ratio feature during a high pressure step and increased deposition on the sidewalls of the feature during at least a low pressure step.

US Patent:

6458255, Oct 1, 2002

Filed:

Jan 25, 2001

Appl. No.:

09/770934

Inventors:

Tony Chiang - Mountain View CA
Peijun Ding - San Jose CA
Barry Chin - Saratoga CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1434

US Classification:

2041925, 20419222

Abstract:

We have discovered that, by depositing a tantalum layer upon a substrate at a temperature of at least 325Â C. , it is possible to obtain an ultra low resistivity which is lower than that previously published in the literature. In addition, it is possible deposit a Ta N film having an ultra low resistivity by depositing the Ta N film upon a substrate at a temperature of at least 275Â C. , wherein x is 1 and y ranges from about 0. 05 to about 0. 18. These films having an ultra low resistivity are obtained at temperatures far below the previously published temperatures for obtaining higher resistivity films. A combination of elevated substrate temperature and ion bombardment of the film surface during deposition enables the use of lower substrate temperatures while maintaining optimum film properties. In another development, we have discovered that the ultra low resistivity tantalum and Ta N films produced by the method of the present invention also exhibit particularly low residual stress, so that they are more stable and less likely to delaminate from adjacent layers in a multilayered semiconductor structure. Further, these films can be chemical mechanical polished at significantly higher rates (at least 40% higher rates) than the higher resistivity tantalum and Ta N films previously known in the industry.

US Patent:

6488823, Dec 3, 2002

Filed:

Nov 4, 1999

Appl. No.:

09/423470

Inventors:

Tony Chiang - San Jose CA
Peijun Ding - San Jose CA
Barry L. Chin - Saratoga CA
Bingxi Sun - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1434

US Classification:

20419215, 20419222

Abstract:

The present disclosure pertains to our discovery that residual stress residing in a tantalum film or tantalum nitride film can be controlled (tuned) during deposition by adjusting at least two particular process variables which have counteracting effects on the residual film stress. By tuning individual film stresses within a film stack, it is possible to balance stresses within the stack. Process variables of particular interest include: power to the sputtering target process chamber pressure (i. e. , the concentration of various gases and ions present in the chamber); substrate DC offset bias voltage (typically an increase in the AC applied substrate bias power); power to an ionization source (typically a coil); and temperature of the substrate upon which the film is deposited. The process chamber pressure and the substrate offset bias most significantly affect the film tensile and compressive stress components, respectively. The most advantageous tuning of a sputtered film is achieved using high density plasma sputter deposition, which provides for particular control over the ion bombardment of the depositing film surface.

US Patent:

6566259, May 20, 2003

Filed:

Nov 9, 2000

Appl. No.:

09/710383

Inventors:

Peijun Ding - San Jose CA
Imran Hashim - San Jose CA
Barry Chin - Saratoga CA
Bingxi Sun - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438687, 438627, 438643, 438646, 438653, 438680, 438688

Abstract:

Metallization process sequences are provided for forming reliable interconnects including lines, vias and contacts. An initial barrier layer, such as Ta or TaN, is first formed on a patterned substrate followed by seed layer formed using high density plasma PVD techniques. The structure is then filled using either 1) electroplating, 2) PVD reflow, 3) CVD followed by PVD reflow, or 4) CVD.