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Barry L Chin

age ~69

from Saratoga, CA

Also known as:
  • Barry Chin
  • Barry Lee Chin
  • Arry Chin
13174 Cumberland Dr, Saratoga, CA 950704087411176

Barry Chin Phones & Addresses

  • 13174 Cumberland Dr, Saratoga, CA 95070 • 4087411176
  • Santa Clara, CA
  • Sunnyvale, CA
  • San Diego, CA

Isbn (Books And Publications)

  • Copper Interconnect Technology

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  • Author:
    Barry Chin
  • ISBN #:
    0819438979
  • Licensed Architect: Building Design Examination Primer

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  • Author:
    Barry Chin
  • ISBN #:
    0933885059
  • Licensed Architect: Building Design Examination Primer

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  • Author:
    Barry Chin
  • ISBN #:
    0933885032

Resumes

Barry Chin Photo 1

Barry Chin

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Us Patents

  • Structure For Improving Low Temperature Copper Reflow In Semiconductor Features

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  • US Patent:
    6352926, Mar 5, 2002
  • Filed:
    Nov 10, 2000
  • Appl. No.:
    09/709991
  • Inventors:
    Peijun Ding - San Jose CA
    Imran Hashim - San Jose CA
    Barry L. Chin - Saratoga CA
  • Assignee:
    Applied Materials, Inc. - Santa Clara CA
  • International Classification:
    H01L 2144
  • US Classification:
    438687, 435734
  • Abstract:
    We have discovered that complete copper filling of semiconductor features such as trenches and vias, without the formation of trapped voids, can be accomplished using a copper reflow process when the unfilled portion of the feature structure prior to reflow comprises a capillary within the feature, wherein the volume of the capillary represents between about 20% and about 90%, preferably between about 20% and about 75% of the original feature volume prior to filling with copper. The aspect ratio of the capillary is preferably at least 1. 5. The maximum opening dimension of the capillary is less than about 0. 8 m. The preferred substrate temperature during the reflow process includes either a soak at an individual temperature or a temperature ramp-up or ramp-down where the substrate experiences a temperature within a range from about 300° C. to about 600° C. , more preferably between about 300° C.
  • Method Of Depositing Low Resistivity Barrier Layers For Copper Interconnects

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  • US Patent:
    20050272254, Dec 8, 2005
  • Filed:
    Jul 18, 2005
  • Appl. No.:
    11/184404
  • Inventors:
    Peijun Ding - Saratoga CA,
    Zheng Xu - Pleasanton CA,
    Hong Zhang - Fremont CA,
    Xianmin Tang - San Jose CA,
    Praburam Gopalraja - San Jose CA,
    Suraj Rengarajan - San Jose CA,
    John Forster - San Francisco CA,
    Jianming Fu - Palo Alto CA,
    Tony Chiang - Campbell CA,
    Gongda Yao - Fremont CA,
    Fusen Chen - Saratoga CA,
    Barry Chin - Saratoga CA,
    Gene Kohara - San Jose CA,
  • Assignee:
    Applied Materials, Inc. - Santa Clara CA
  • International Classification:
    H01L021/4763
    H01L021/44
  • US Classification:
    438628000, 438629000
  • Abstract:
    We have discovered a method of providing a thin approximately from about 2 Å to about 100 Å thick Taseed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the Taseed layer. Further, the Taseed layer exhibits low resistivity, in the range of 30 μΩ cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface form the Taseed layer. In another embodiment of the method, a Ta film is altered on its surface to form the Taseed layer.
  • Ion Implantation Of Thin Film Crsi.sub.2 And Sic Resistors

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  • US Patent:
    47598360, Jul 26, 1988
  • Filed:
    Aug 12, 1987
  • Appl. No.:
    7/084541
  • Inventors:
    Lorimer K. Hill - Cupertino CA
    Barry L. Chin - Sunnyvale CA
    Richard A. Blanchard - Los Altos CA
  • Assignee:
    Siliconix Incorporated - Santa Clara CA
  • International Classification:
    B05D 512
    B05D 306
    H01C 1706
  • US Classification:
    20419221
  • Abstract:
    A thin film resistor is formed using sputtering to deposit a thin film of resistive material on an insulating surface. The sputter target is composed of constituents which are normally present in relatively large quantities in thin film resistors, such as chromium silicide and silicon carbide. The sputtered thin film material is formed into resistor regions. An insulating layer is deposited over the thin film material. Ions (e. g. , boron ions) are then implanted into the thin film through the insulating layer. These implanted constituents have a significant effect on the temperature coefficient and sheet resistance of the thin film resistor. Ion implantation of these constituents enables more control over the characteristics of the thin film resistor as compared to prior art techniques not using ion implantation.
  • Copper Alloy Via Structure

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  • US Patent:
    61603155, Dec 12, 2000
  • Filed:
    Jan 6, 2000
  • Appl. No.:
    9/478721
  • Inventors:
    Tony Chiang - Mountain View CA
    Peijun Ding - San Jose CA
    Barry Chin - Saratoga CA
    Imran Hashim - Sunnyvale CA
    Bingxi Sun - Sunnyvale CA
  • Assignee:
    Applied Materials, Inc. - Santa Clara CA
  • International Classification:
    H01L 2348
  • US Classification:
    257762
  • Abstract:
    A copper via structure formed when copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide but also extends into the oxide a distance of about 100 nm. The alloying metal oxide having a thickness of about 6 nm on the oxide sidewalls encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.
  • Printed Chemical Mechanical Polishing Pad

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  • US Patent:
    20130283700, Oct 31, 2013
  • Filed:
    Aug 21, 2012
  • Appl. No.:
    13/591051
  • Inventors:
    Rajeev Bajaj - Fremont CA,
    Barry Lee Chin - Saratoga CA,
    Terrance Y. Lee - Oakland CA,
  • International Classification:
    B24D 3/28
  • US Classification:
    51295
  • Abstract:
    A method of fabricating a polishing layer of a polishing pad includes successively depositing a plurality of layers with a 3D printer, each layer of the plurality of polishing layers deposited by ejecting a pad material precursor from a nozzle and solidifying the pad material precursor to form a solidified pad material.
  • Graphene Deposition

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  • US Patent:
    20110303899, Dec 15, 2011
  • Filed:
    Jun 10, 2011
  • Appl. No.:
    13/158186
  • Inventors:
    Deenesh Padhi - Sunnyvale CA,
    Jacob Janzen - Redwood City CA,
    Shahid Shaikh - Santa Clara CA,
    Bok Hoen Kim - San Jose CA,
    Barry Chin - Saratoga CA,
  • Assignee:
    Applied Materials, Inc. - Santa Clara CA
  • International Classification:
    H01L 21/20
    H01L 29/16
  • US Classification:
    257 29, 438478, 257E2109, 257E29082
  • Abstract:
    Embodiments of the invention are directed toward the deposition of Graphene on a semiconductor substrate. In some embodiments, these processes can occur at low temperature levels during a back end of the line process. For example, Graphene can be deposited in a CVD reactor at a processing temperature that is below 600° C. to protect previously deposited layers that may be susceptible to sustained higher temperatures. Graphene deposition can include the deposition of an underlayer (e.g., cobalt) followed by the flow of a carbon precursor (e.g., acetylene) at the processing temperature. Graphene can then be synthesized with during cooling, an RTP cure, and/or a UV cure.
  • Method Of Depositing A Diffusion Barrier Layer Which Provides An Improved Interconnect

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  • US Patent:
    20090053888, Feb 26, 2009
  • Filed:
    Oct 20, 2008
  • Appl. No.:
    12/288540
  • Inventors:
    Peijun Ding - Saratoga CA,
    Zheng Xu - Plesanton CA,
    Hong Zhang - Fremont CA,
    Xianmin Tang - San Jose CA,
    Praburam Gopalraja - San Jose CA,
    Suraj Rengarajan - San Jose CA,
    John C. Forster - San Francisco CA,
    Jianming Fu - Palo Alto CA,
    Tony Chiang - Santa Clara CA,
    Gongda Yao - Fremont CA,
    Fusen E. Chen - Saratoga CA,
    Barry L. Chin - Saratoga CA,
    Gene Y. Kohara - Fremont CA,
  • International Classification:
    H01L 21/4763
    H01L 21/31
  • US Classification:
    438627, 438785, 257E21169
  • Abstract:
    A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer.
  • Damage-Free Sculptured Coating Deposition

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  • US Patent:
    20070178682, Aug 2, 2007
  • Filed:
    Apr 10, 2007
  • Appl. No.:
    11/733671
  • Inventors:
    Tony Chiang - Mountain View CA,
    Gongda Yao - Fremont CA,
    Peijun Ding - San Jose CA,
    Fusen Chen - Cupertino CA,
    Barry Chin - Saratoga CA,
    Gene Kohara - Fremont CA,
    Zheng Xu - Foster City CA,
    Hong Zhang - Fremont CA,
  • International Classification:
    H01L 21/20
  • US Classification:
    438584000
  • Abstract:
    We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

News

Moderna: From startup to $25 billion biotech developing coronavirus vaccine

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  • ambridge that academics who want to take the leap into industry should talk to Langer. Portrait of Robert Langer in his Cape Cod residence in North Falmouth, MA on April 25, 2020. Barry Chin/The Boston Globe/Getty Images
  • Date: May 23, 2020
  • Category: More news
  • Source: Google

Youtube

Dr. Barry Cohen Chin Implant/Augmentation Vid...

Dr. Barry J. Cohen walks you through the benefits and risks of a Chin ...

  • Category:
    Education
  • Uploaded:
    22 Jul, 2008
  • Duration:
    2m 17s

Everybody was Kung-Fu Fighting: Chin Style

Everybody was Kung-Fu Fighting: Chin Style Song by Carl Douglas Starri...

  • Category:
    Comedy
  • Uploaded:
    23 Jul, 2008
  • Duration:
    1m 22s

Barry Chin on sports photojournalism

Boston, MA - Journalism and Writing Workshop OCA - New England Chapter...

  • Category:
    Nonprofits & Activism
  • Uploaded:
    29 Jul, 2009
  • Duration:
    2m 35s

this is barry chin

the morning after campout, god knows how this all started lmao

  • Category:
    Comedy
  • Uploaded:
    25 Aug, 2008
  • Duration:
    34s

Jon Huntsman explores GOP run in New Hampshire

(Boston Globe) Jon Huntsman, Obama's former ambassador to China, explo...

  • Category:
    News & Politics
  • Uploaded:
    20 May, 2011
  • Duration:
    58s

Death and the Powers: The Robots' Opera

(Boston Globe) MIT Media Lab creates the robots for the opera, Death a...

  • Category:
    News & Politics
  • Uploaded:
    11 Mar, 2011
  • Duration:
    17m 38s

Cat grader leaving to port from Barry Chin's ...

Heavy Equipment Transport. Cat grader being transported to port of Mia...

  • Category:
    Autos & Vehicles
  • Uploaded:
    23 Oct, 2010
  • Duration:
    1m 30s

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Googleplus

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Classmates

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Barry Chin

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Schools:
Emerson Middle School Lakewood OH 1972-1974
Community:
Francine Drake
Barry Chin Photo 15

Barry Chin

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Schools:
Hillcrest High School Ottawa Morocco 1978-1982
Community:
Susan Dart, Pat Godding

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