Bang-Thu Nguyen from 2877 Kearney Ave, Santa Clara, CA 95051, Phone: 4082472198

Apparatus And Method For Testing Of Stacked Die Structure
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US Patent:

8063654, Nov 22, 2011
Filed:

Jul 17, 2009
Appl. No.:

12/505215
Inventors:

Arifur Rahman - San Jose CA, US
Bang-Thu Nguyen - Santa Clara CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G01R 31/26
US Classification:

32476203, 32476206
Abstract:

An integrated circuit device includes a stacked die and a base die having probe pads that directly couple to test logic of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. The base die also includes a first probe pad configured to couple test input, a second probe pad configured to couple test output, and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die to implement the scan chain. The probe pads are coupled directly to the test logic such that configuration of the programmable logic is not required to implement the scan chain.

System And Method For Detecting Mask Data Handling Errors
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US Patent:

8266553, Sep 11, 2012
Filed:

Jun 18, 2008
Appl. No.:

12/141543
Inventors:

Bang-Thu Nguyen - Santa Clara CA, US
Yan Wang - San Jose CA, US
Xin Wu - Fremont CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 51
Abstract:

An integrated circuit device layout and a method for detecting mask data handling errors are disclosed in which integrated circuit device layout includes a device region in which operable circuitry is disposed. Integrated circuit device layout also includes a verification region in which verification elements are disposed. The verification elements include cells that are duplicates of at least some of the different types of cells in device region and can include structures that are duplicates of at least some of the types of structures in the device region. The patterns in verification region are used in the final verification process to identify mask data handling errors in a mask job deck. Because the patterns in verification region are easy to locate and identify, the time required to perform the final verification process is reduced and the chance of error in the final verification process is reduced.

Integrated Circuit With Stress Inserts
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US Patent:

8350253, Jan 8, 2013
Filed:

Jan 29, 2010
Appl. No.:

12/697027
Inventors:

Bei Zhu - Los Gatos CA, US
Bang-Thu Nguyen - Santa Clara CA, US
Qi Lin - Cupertino CA, US
Zhiyuan Wu - San Jose CA, US
Ping-Chin Yeh - San Jose CA, US
Yun Wu - San Jose CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

H01L 29/06
US Classification:

257 19, 257E29193
Abstract:

An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.

Mitigation Of Well Proximity Effect In Integrated Circuits
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US Patent:

8350365, Jan 8, 2013
Filed:

Jan 13, 2011
Appl. No.:

13/005680
Inventors:

Yun Wu - San Jose CA, US
Qi Lin - Cupertino CA, US
Bang-Thu Nguyen - Santa Clara CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

H01L 21/4763
US Classification:

257632, 257635, 257638, 257E21495, 438510, 438514, 438942
Abstract:

A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.

Method And Apparatus For Compensating An Integrated Circuit Layout For Mechanical Stress Effects
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US Patent:

7673270, Mar 2, 2010
Filed:

Mar 13, 2007
Appl. No.:

11/717811
Inventors:

Yan Wang - Campbell CA, US
Nui Chong - Cupertino CA, US
Bang-Thu Nguyen - Santa Clara CA, US
Jonathan Jung-Ching Ho - Fremont CA, US
Qi Lin - Cupertino CA, US
Yuhao Luo - San Jose CA, US
Hing Yee Angela Wong - San Jose CA, US
Xin X. Wu - Fremont CA, US
Yuezhen Fan - San Jose CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 12, 716 1, 716 11
Abstract:

Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.

Method And Apparatus For Suppressing Metal-Gate Cross-Diffusion In Semiconductor Technology
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US Patent:

20150054085, Feb 26, 2015
Filed:

Aug 22, 2013
Appl. No.:

13/973616
Inventors:

- San Jose CA, US
Yun Wu - San Jose CA, US
Bang-Thu Nguyen - Santa Clara CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

H01L 27/092
H01L 21/8238
US Classification:

257369, 438233
Abstract:

An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region.