Bala Reddy Thumma

US Patent:

60145064, Jan 11, 2000

Filed:

Mar 21, 1996

Appl. No.:

8/621742

Inventors:

Moazzem Hossain - San Jose CA
Bala Thumma - Milpitas CA
Sunil Ashtaputre - San Jose CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

39550012

Abstract:

A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (A) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (B) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (C) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (a) modifying the netlist pursuant to an engineering change order (ECO); and (b) making an ECO placement of at least one cell into the layout area by (i) picking an unplaced cell from a set of unplaced cells to be a picked cell; (ii) determining a target window within said layout area for the placement of said picked cell; (iii) mapping said picked cell inside said target window; (iv) removing said picked cell from said set of unplaced cells; (v) optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to other cells, and modifying said placement of said picked cell if it improves timing; and (vi) repeating steps (i)-(v) until said set of unplaced cells is empty. A layout tool implements the method on a computer system to form a portion of an integrated circuit fabrication system.

US Patent:

59532360, Sep 14, 1999

Filed:

Oct 31, 1995

Appl. No.:

8/550848

Inventors:

Moazzem Hossain - San Jose CA
Bala Thumma - Milpitas CA
Sunil Ashtaputre - San Jose CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 1700
G06F 1750

US Classification:

364491

Abstract:

A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (a) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (b) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (c) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (i) modifying the netlist pursuant to an engineering change order (ECO); and (ii) making an ECO placement of at least one cell into the layout area based upon the timing constraints while adjusting any affected nets as specified by the netlist. A layout tool implements the method on a computer system to form a portion of and integrated circuit fabrication system.