Bala Chandran Padmakumar

US Patent:

7656027, Feb 2, 2010

Filed:

May 30, 2006

Appl. No.:

11/443669

Inventors:

Carlos Dangelo - Los Gatos CA, US
Bala Padmakumar - Mountain View CA, US

Assignee:

Nanoconduction, Inc. - Menlo Park CA

International Classification:

H01L 23/34

US Classification:

257713, 257276, 257E21407, 174250, 361780, 438122

Abstract:

An in-chip system and method for removing heat from integrated circuits is disclosed. One embodiment is a substrate with a front side and a back side. The front side of the substrate is capable of having formed thereon a plurality of transistors. A plurality of structures within the substrate contain a solid heat conductive media comprising carbon nanotubes and/or a metal, such as copper. At least some of the plurality of structures extend from the back side of the substrate into the substrate. In some embodiments, the carbon nanotubes are formed within the substrate using a catalyst.

US Patent:

8080871, Dec 20, 2011

Filed:

Jul 22, 2008

Appl. No.:

12/177815

Inventors:

Carlos Dangelo - Los Gatos CA, US
Ephraim Suhir - Los Altos CA, US
Subrata Dey - Fremont CA, US
Barbara Wacker - Saratoga CA, US
Yuan Xu - Milpitas CA, US
Arthur Boren - San Jose CA, US
Darin Olsen - Menlo Park CA, US
Yi Zhang - Sunnyvale CA, US
Peter Schwartz - Livermore CA, US
Bala Padmakumar - Mountain View CA, US

Assignee:

Samsung Electronics Co., Ltd. - Gyeonggi-Do

International Classification:

H01L 23/34

US Classification:

257720, 257E23101, 257E23105, 257706, 257778, 438108, 438122, 438125, 977742, 977762

Abstract:

One aspect of the invention includes a copper substrate; a catalyst on top of the copper substrate surface; and a thermal interface material that comprises a layer containing carbon nanotubes that contacts the catalyst. The carbon nanotubes are oriented substantially perpendicular to the surface of the copper substrate. A Raman spectrum of the layer containing carbon nanotubes has a D peak at 1350 cmwith an intensity ID, a G peak at 1585 cmwith an intensity IG, and an intensity ratio I/Iof less than 0. 7 at a laser excitation wavelength of 514 nm. The thermal interface material has: a bulk thermal resistance, a contact resistance at an interface between the thermal interface material and the copper substrate, and a contact resistance at an interface between the thermal interface material and a solid-state device. A summation of these resistances has a value of 0. 06 cmK/W or less.

US Patent:

49868780, Jan 22, 1991

Filed:

Jul 19, 1988

Appl. No.:

7/221310

Inventors:

Alp Malazgirt - Fremont CA
Bala Padmakumar - Sunnyvale CA
Arya Bhattacherjee - Fremont CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H01L 21306

US Classification:

156643

Abstract:

A method of manufacturing an integrated circuit having a multilayer structure where the method includes the steps of depositing a thin layer of low temperature oxide (LTO) on top of conductors and then spinning and curing a thin layer of spin-on-glass to planarize the surface of the device. This structure is then plasma etched to remove the spin-on-glass and a portion of the LTO at approximately the same rate. The structure is then dipped in a mild potassium hydroxide solution to completely remove the SOG material, even from the crevices and gaps which are present on the surface. This enables the device to be manufactured free of any organic substances from the SOG in the body of the structure. A passivation layer can now be deposited to protect the underlying circuitry from ionic contamination, water vapor penetration and handling.