Badruddin N Agarwala

US Patent:

20140019923, Jan 16, 2014

Filed:

Jul 12, 2013

Appl. No.:

13/941234

Inventors:

Badruddin Agarwala - Pleasanton CA, US
Tarak Parikh - San Jose CA, US
Vivek Bhat - San Jose CA, US
Neeraj Joshi - Fremont CA, US

Assignee:

MENTOR GRAPHICS CORPORATION - Wilsonville OR

International Classification:

G06F 17/50

US Classification:

716104

Abstract:

This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding to at least portions of the library components, which are interconnected with trace lines based, at least in part, on the messages. The debug tool can prompt display of the schematic representation of the test bench.

US Patent:

20140019924, Jan 16, 2014

Filed:

Jul 11, 2013

Appl. No.:

13/940082

Inventors:

Badruddin Agarwala - Pleasanton CA, US
Tarak Parikh - San Jose CA, US
Vivek Bhat - San Jose CA, US
Neeraj Joshi - Fremont CA, US

Assignee:

MENTOR GRAPHICS CORPORATION - Wilsonville OR

International Classification:

G06F 17/50

US Classification:

716106

Abstract:

This application discloses a debug tool to prompting display of at least a portion of a simulated output for a circuit design in a debug window, identifying a marker corresponding to a value in the simulated output has been specified for the debug environment, and prompting accentuation of one or more occurrences of the value in the debug window relative to other values in the simulated output based, at least in part, on the marker specified for the debug environment.

US Patent:

20140005999, Jan 2, 2014

Filed:

Jun 21, 2013

Appl. No.:

13/924156

Inventors:

BADRUDDIN AGARWALA - Pleasanton CA, US
Tarak Parikh - San Jose CA, US
Vivek Bhat - San Jose CA, US
Neeraj Joshi - Fremont CA, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 17/50

US Classification:

703 14

Abstract:

This application discloses a design verification tool to simulate a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design. The design verification tool can determine whether the simulated output for the circuit design is different than an expected output for the circuit design. A debug tool can synchronize the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.