Asit S Ambekar

Address:

9505 Savannah Rdg Dr, Austin, TX 78726

VIN:

5FNYF18527B002450

Make:

HONDA

Model:

PILOT

Year:

2007

US Patent:

7750511, Jul 6, 2010

Filed:

Apr 10, 2007

Appl. No.:

11/733435

Inventors:

Vikas Agarwal - Austin TX, US
Asit S. Ambekar - Austin TX, US
Sanjay Dubey - Austin TX, US
Saiful Islam - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H 3/00

US Classification:

307131

Abstract:

An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained. Because of the self-contained nature of the decoupling capacitor circuit, an integrated circuit may contain an array of decoupling capacitor circuits without expenditure of substantial chip real estate for respective decoupling capacitor control lines.

US Patent:

20040215936, Oct 28, 2004

Filed:

Apr 23, 2003

Appl. No.:

10/422021

Inventors:

Asit Ambekar - Austin TX, US
Dung Nguyen - Austin TX, US
Raymond Yeung - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/30

US Classification:

712/217000

Abstract:

A single rename register array is used in an SMT processor. Two bits are added to each register address of the rename register array, one for bit for thread zero (CTB) and one bit for thread one (CTB). The CTB bits are all set to a logic value on power on or start-up. A control instruction (CI) that sets control bits used by other instructions is assigned a register in the rename register array having an address designated as pointer (PTR) address. When a control instruction with an assigned entry with PTR address M completes, then the CTB bit at the PTR address M is flipped to its opposite logic state; likewise, its Valid bit is set to a “not” Valid state. The self resetting CTB bit is used to determine whether an issued instruction sources a register in the rename register array or a corresponding architected register.