Asao Yamashita

US Patent:

7097779, Aug 29, 2006

Filed:

Jul 6, 2004

Appl. No.:

10/883784

Inventors:

Aelan Mosden - Poughkeepsie NY, US
Asao Yamashita - Wappingers Falls NY, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

B44C 1/22
H01L 21/00

US Classification:

216 37, 216 2, 216 41, 216 58, 216 67, 216 69, 438694, 438710

Abstract:

A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.

US Patent:

7209798, Apr 24, 2007

Filed:

Sep 20, 2004

Appl. No.:

10/944463

Inventors:

Asao Yamashita - Wappingers Falls NY, US
Merritt Lane Funk - Austin TX, US
Daniel Prager - Hopewell Junction NY, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G06F 19/00

US Classification:

700121, 738714

Abstract:

This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.

US Patent:

7292906, Nov 6, 2007

Filed:

Jul 14, 2004

Appl. No.:

10/890410

Inventors:

Merritt Funk - Austin TX, US
Kevin Augustine Pinto - Austin TX, US
Asao Yamashita - Wappingers Falls NY, US
Wesley Natzle - New Paltz NY, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G06F 19/00
H01L 21/302

US Classification:

700121, 438689

Abstract:

A processing method of processing a substrate is presented that includes: receiving pre-process data, wherein the pre-process data comprises a desired process result and actual measured data for the substrate; determining a required process result, wherein the required process result comprises the difference between the desired process result and the actual measured data; creating a new process recipe by modifying a nominal recipe obtained from a processing tool using at least one of a static recipe and a formula model, wherein the new process recipe provides a new process result that is approximately equal to the required process result; and sending the new process recipe to the processing tool and the substrate.

US Patent:

7328418, Feb 5, 2008

Filed:

Feb 1, 2005

Appl. No.:

11/046903

Inventors:

Asao Yamashita - Wappingers Falls NY, US
Merritt Funk - Austin TX, US
Daniel Prager - Hopewell Junction NY, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 10, 716 1, 716 19

Abstract:

This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherein the nested structures/features need to be reduced relative to the isolated structures/features, while allowing for the critical control of trimming.

US Patent:

7527016, May 5, 2009

Filed:

Jul 10, 2003

Appl. No.:

10/615915

Inventors:

Yohei Yamazawa - Nirasaki, JP
Manabu Iwata - Nirasaki, JP
Chishio Koshimizu - Nirasaki, JP
Fumihiko Higuchi - Beverly MA, US
Akitaka Shimizu - Nirasaki, JP
Asao Yamashita - Hopewell Junction NY, US
Nobuhiro Iwama - Nirasaki, JP
Tsutomu Higashiura - Nirasaki, JP
Dongsheng Zhang - Tokyo, JP
Michiko Nakaya - Nirasaki, JP
Norikazu Murakami - Nirasaki, JP

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

C23C 16/00
C23F 1/00
H01L 21/306
H05B 31/26

US Classification:

118723E, 15634543, 15634544, 15634547, 31511121

Abstract:

An apparatus, which performs a plasma process on a target substrate by using plasma, includes first and second electrodes in a process chamber to oppose each other. An RF field, which turns a process gas into plasma by excitation, is formed between the first and second electrodes. An RF power supply, which supplies RF power, is connected to the first or second electrode through a matching circuit. The matching circuit automatically performs input impedance matching relative to the RF power. A variable impedance setting section is connected to a predetermined member, which is electrically coupled with the plasma, through an interconnection. The impedance setting section sets a backward-direction impedance against an RF component input to the predetermined member from the plasma. A controller supplies a control signal concerning a preset value of the backward-direction impedance to the impedance setting section.

US Patent:

7713758, May 11, 2010

Filed:

Jun 13, 2007

Appl. No.:

11/762258

Inventors:

Asao Yamashita - Fishkill NY, US
Merritt Funk - Austin TX, US
Daniel Prager - Hopewell Junction NY, US
Lee Chen - Cedar Creek TX, US
Radha Sundararajan - Dripping Springs TX, US

Assignee:

Tokyo Electon Limited - Tokyo

International Classification:

H01L 21/00

US Classification:

438 9, 438706, 438710, 438714, 700121

Abstract:

The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures.

US Patent:

7763404, Jul 27, 2010

Filed:

Sep 26, 2006

Appl. No.:

11/535247

Inventors:

James E. Willis - Buellton CA, US
Manuel Perez - Martinsville NJ, US
Asao Yamashita - Fishkill NY, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G03F 9/00

US Classification:

430 30, 430 5, 430311

Abstract:

The present invention provides methods and system for improving the accuracy of measurements made using optical metrology. The present invention relates to methods and systems for changing the optical properties of tunable resists that can be used in the production of electronic devices such as integrated circuits. Further, the invention provides methods and systems for using a modifiable resist layer that provides a first set of optical properties before exposure and a second set of optical properties after exposure.

US Patent:

7765077, Jul 27, 2010

Filed:

Sep 21, 2007

Appl. No.:

11/859596

Inventors:

Asao Yamashita - Fishkill NY, US
Merritt Funk - Austin TX, US
Daniel J. Prager - Hopewell Junction NY, US
Lee Chen - Cedar Creek TX, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G01D 18/00

US Classification:

702 85

Abstract:

The invention can provide a method of processing a substrate using Spacer-Optimization (S-O) processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures. In addition, the S-O processing sequences can include one or more deposition procedures, one or more partial-etch procedures, one or more chemical oxide removal (COR)-etch procedures, one or more optimization procedures, one or more evaluation procedures, and/or one or more verification procedures.