Arvind Pruthi

US Patent:

7809692, Oct 5, 2010

Filed:

Jan 31, 2007

Appl. No.:

11/701010

Inventors:

Arvind Pruthi - Sunnyvale CA, US
Kiyoshi Komatsu - San Mateo CA, US

Assignee:

Network Appliance, Inc. - Sunnyvale CA

International Classification:

G06F 17/30

US Classification:

707674, 707675, 707676, 707677, 707678, 707680

Abstract:

A method and system for generating and restoring a backup image are disclosed. According to one aspect of the invention, a server receives a request to generate a backup image. The request includes a selection a backup path. Based on the backup path, the server generates a list of files and/or directories to backup. However, before writing the files to the backup image, the server generates an offset map to indicate where in the backup image each file will be located. The server then writes the offset map to the backup image. During a restore operation, the server receives a request to restore files, including a selection of files and/or directories to restore. The server reads the offset map from the beginning of the backup image to quickly determine the location in the backup image of selected files.

US Patent:

8219887, Jul 10, 2012

Filed:

Nov 20, 2008

Appl. No.:

12/274874

Inventors:

Arvind Pruthi - Los Gatos CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

G11C 29/00

US Classification:

714769, 714 52

Abstract:

The parallel RS-RAID data storage architecture can aggregate that data and checksums within each cluster into intermediate or partial sums that are transferred or distributed to other clusters. The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture.

US Patent:

8359524, Jan 22, 2013

Filed:

Jun 29, 2012

Appl. No.:

13/537828

Inventors:

Arvind Pruthi - Los Gatos CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

G11C 29/00

US Classification:

714769, 714 52, 714767

Abstract:

The parallel RS-RAID data storage architecture can aggregate that data and checksums within each cluster into intermediate or partial sums that are transferred or distributed to other clusters. The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture.

US Patent:

8473680, Jun 25, 2013

Filed:

Sep 14, 2010

Appl. No.:

12/881459

Inventors:

Arvind Pruthi - Los Gatos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711118

Abstract:

A system includes a counting module, a region defining module, and a caching module. The counting module is configured to count a first number of accesses to a first region of a storage medium during a first time period. The counting module is configured to count a second number of accesses to the first region during a second time period following the first time period. The region defining module is configured to selectively define a second region and a third region within the first region when the second number of accesses is greater than the first number of accesses by a predetermined amount. The caching module is configured to selectively cache the second region into a cache memory when a third number of accesses to the second region during a third time period following the second time period is greater than a fourth number of accesses to the third region during the third time period.

US Patent:

8539162, Sep 17, 2013

Filed:

Feb 23, 2011

Appl. No.:

13/033569

Inventors:

Arvind Pruthi - Los Gatos CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

G06F 12/00

US Classification:

711133, 711137, 711E12057

Abstract:

Methods and systems for quantifying a spatial distribution of accesses to storage systems and for determining spatial locality of references to storage addresses in the storage systems are described. In one aspect, a specified quantity of address references associated with a storage system is received. A spatial distribution of references to addresses of the storage system is determined based at least in part on the received specified quantity of the address references, and the determined spatial distribution is combined with a previously determined spatial distribution into a spatial locality metric of the storage system. The spatial locality metric includes a weighted sum of the determined spatial distribution and the previously determined spatial distribution. The spatial locality metric is used in caching data from the storage system to a cache device.

US Patent:

8566534, Oct 22, 2013

Filed:

Apr 1, 2011

Appl. No.:

13/078359

Inventors:

Arvind Pruthi - Los Gatos CA, US
Sandeep Karmarkar - Pune, IN

Assignee:

Marvell International Ltd - Hamilton

International Classification:

G06F 12/00

US Classification:

711141

Abstract:

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, to manage an address space for large caches are described. In some implementations, a method includes receiving data to be cached in a cache address space associated with a cache memory. The cache address space includes two or more designated portions of the cache address space, such that each of the two or more designated portions has an associated minimum amount of data allowed to be cached therein. Additionally, the respective minimum amounts of the two or more designated portions are different from each other. The method also includes selecting a cache address for caching the received data from one of the two or more designated portions of the cache address space that has an associated minimum amount of data allowed to be cached therein being less than the received data. Further, the method includes caching the received data at the selected cache address, and accessing at least a subset of the data cached at the selected cache address.

US Patent:

8583893, Nov 12, 2013

Filed:

May 26, 2010

Appl. No.:

12/788097

Inventors:

Arvind Pruthi - Los Gatos CA, US
Shailesh P. Parulekar - Pune, IN
Mayur Shardul - Pune, IN

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

G06F 12/00

US Classification:

711207, 711136, 711216, 711173

Abstract:

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, manage metadata for virtual volumes. In some implementations, a method and system include defining multiple metadata blocks in a persistent storage, including information that links a virtual address space to the storage system, where the defining includes, for at least one of the multiple metadata blocks, determining multiple output addresses corresponding to the storage system, and writing the multiple output addresses and an identifier corresponding to the multiple metadata blocks in a metadata block in the persistent storage. In some implementations, a method and system include reading the multiple metadata blocks into the memory from the persistent storage, including identifying the metadata block based on the identifier; receiving an input address of the virtual address space; and obtaining a corresponding output address to the storage system using the multiple metadata blocks in the memory.

US Patent:

8639868, Jan 28, 2014

Filed:

Jul 12, 2011

Appl. No.:

13/181322

Inventors:

Arvind Pruthi - Los Gatos CA, US
Ram Kishore Johri - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

G06F 13/00
G06F 13/28

US Classification:

710301, 711138

Abstract:

The present disclosure includes systems and techniques relating to customization of a bus adapter card. In some implementations, an apparatus includes a processor and a program memory, a bus adapter card coupled with the computing apparatus and configured to connect with a storage device, the bus adapter card comprising a cache memory and a controller to cache in the cache memory data associated with the storage device, where the program memory includes a driver to communicate with the bus adapter card responsive to requests corresponding to the storage device, and the driver is configured to modify its communications with the bus adapter card responsive to information provided separate from the requests.