Andrew B Kahng

Author:

Andrew B. Kahng

ISBN #:

0792394836

US Patent:

7062743, Jun 13, 2006

Filed:

Sep 24, 2003

Appl. No.:

10/670134

Inventors:

Andrew B. Kahng - Del Mar CA, US
Christoph Albrecht - Berkeley CA, US
Ion I. Mandoiu - Storrs CT, US
Alexander Z. Zelikovsky - Roswell GA, US

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

G06F 17/50

US Classification:

716 13, 716 12

Abstract:

A method and system for evaluating a floorplan and for defining a global buffered routing for an integrated circuit including constructing a graphical representation of the integrated circuit floorplan, including wire capacity and buffer capacity; formulating an integer linear program from said graphical representation; finding a solution to said integer linear program.

US Patent:

7441211, Oct 21, 2008

Filed:

Jun 3, 2005

Appl. No.:

11/145025

Inventors:

Puneet Gupta - Sunnyvale CA, US
Andrew B Kahng - Del Mar CA, US

Assignee:

Blaze DFM, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 1, 716 5, 716 6

Abstract:

Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.

US Patent:

7627849, Dec 1, 2009

Filed:

Mar 21, 2006

Appl. No.:

11/386268

Inventors:

Puneet Gupta - Santa Clara CA, US
Andrew B. Kahng - Del Mar CA, US

Assignee:

Tela Innovations, Inc. - Campbell CA

International Classification:

G06F 17/50

US Classification:

716 21, 716 20

Abstract:

A method for improving a resolution enhanced (RE) layout produced by an RE program that starts with a nominal integrated circuit layout. For at least one feature of said layout at least one critical feature quality is chosen from a set of feature qualities and at least one starting condition of said resolution enhancement program is adjusted in response to said at least one critical feature quality.

US Patent:

7640522, Dec 29, 2009

Filed:

Jan 14, 2006

Appl. No.:

11/331605

Inventors:

Puneet Gupta - Santa Clara CA, US
Andrew B. Kahng - Del Mar CA, US

Assignee:

Tela Innovations, Inc. - Campbell CA

International Classification:

G06F 17/50
G03F 1/00

US Classification:

716 9, 716 3, 716 4, 716 5, 716 21, 430 5

Abstract:

A method and system for detailed placement of layout objects in a standard-cell layout design are disclosed. Layout objects comprise cells and etch dummies. The method includes a programming based technique to calculate layout object perturbation distances for the layout objects. The method includes adjusting the layout objects with their corresponding layout object perturbation distances. This leads to improved photolithographic characteristics such as reduced Critical Dimension (CD) errors and forbidden pitches in the standard-cell layout.

US Patent:

7676772, Mar 9, 2010

Filed:

Jul 13, 2006

Appl. No.:

11/486936

Inventors:

O. Samuel Nakagawa - Redwood City CA, US
Andrew B. Kahng - Del Mar CA, US
Pakman Wong - Cupertino CA, US

Assignee:

Tela Innovations, Inc. - Campbell CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 8

Abstract:

Computer readable media hosting a layout description of electric circuitry that includes a description of prospective fill units and includes characteristic data noting at least one characteristic of each fill unit. In one preferred embodiment, each prospective fill unit includes just a single prospective fill element. Also, in a preferred embodiment, said characteristic data includes effect on electrical characteristics of nearby electrical circuitry. These electrical characteristics may further include timing characteristics and capacitance characteristics. The effect on the thickness of nearby connective elements also may be noted.

US Patent:

7716612, May 11, 2010

Filed:

Nov 20, 2006

Appl. No.:

11/602043

Inventors:

Puneet Gupta - Santa Clara CA, US
Andrew Kahng - Del Mar CA, US
Saumil Shah - San Jose CA, US

Assignee:

Tela Innovations, Inc. - Campbell CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 17, 716 18, 703 16

Abstract:

A method and system for integrated circuit optimization to improve performance and to reduce leakage power consumption of an integrated circuit (IC). The original IC includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. The method creates an optimized standard-cell library from a standard-cell library. The standard-cell library includes a plurality of nominal cells, and each of the nominal cells includes a plurality of transistors. Further, an optimized IC is generated by using the optimized standard-cell library from the original IC. The optimized IC has an improved performance and reduced leakage power characteristics, as compared to the original IC.

US Patent:

7730432, Jun 1, 2010

Filed:

Mar 28, 2006

Appl. No.:

11/391771

Inventors:

Puneet Gupta - Santa Clara CA, US
Andrew Kahng - Del Mar CA, US
Dave Reed - Los Altos CA, US

Assignee:

Tela Innovations, Inc. - Campbell CA

International Classification:

G06F 17/50

US Classification:

716 2, 716 1, 716 9, 716 19

Abstract:

The present invention provides a method and system for designing an integrated circuit (IC). The IC comprises a plurality of cells, and each of the cells comprises a plurality of transistors. The method achieves a target objective of a transistor, of a cell, or of part of or the entire IC. The method of designing the IC includes reshaping a basic shape of the transistor. The method includes determining a reshaping bias solution of the transistor. The method further includes modifying the basic shape of the transistor channel, based on the reshaping bias solution, and preparing a reshaped layout design.

US Patent:

7743349, Jun 22, 2010

Filed:

Oct 19, 2005

Appl. No.:

11/254643

Inventors:

Puneet Gupta - Santa Clara CA, US
Andrew B Kahng - Del Mar CA, US

Assignee:

Tela Innovations, Inc. - Campbell CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 2, 716 5, 716 19, 716 20, 716 21, 703 13, 430 5, 430 30

Abstract:

The present invention provides a method and a system for designing an integrated circuit comprising a plurality of elements. The method includes obtaining a lithography-simulated layout corresponding to at least one element. The lithography-simulated layout accounts for lithography effects on the element. The method further includes determination of an equivalent circuit representation that is compatible to a circuit analysis tool, corresponding to the lithography-simulated layout with respect to one or more performance characteristics and based on user preferences. The method also provides equivalent circuit representation to the circuit analysis tool that analyzes one or more performance characteristics of the elements.