Andrew E Franklin

US Patent:

6563730, May 13, 2003

Filed:

Apr 9, 2002

Appl. No.:

10/119191

Inventors:

Hengyang Lin - San Jose CA
Andrew J. Franklin - Santa Clara CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G11C 1100

US Classification:

365154, 36518901

Abstract:

A static RAM bit cell and a system and method for operating an array of such static RAM bit cells. The static RAM bit cell herein includes a cell of four transistors configured to store data. It also includes a pair of word line pass transistors and a pair of column pass transistors coupled to the cell of four transistors. The word line pass transistors are coupled to a word line such that they can be opened in closed in response to a signal on the word line. The column pass transistors are coupled to a column select transistor such that they can be opened and closed in response to a signal on the column select line. Using this configuration signals can be generated on the word line and the column select line so that only a small fraction of the total number of static RAM bit cells in an array need to be charged and discharged in connection with performing read and write operations to a specific static RAM bit cell.

US Patent:

6618282, Sep 9, 2003

Filed:

Aug 7, 2002

Appl. No.:

10/213845

Inventors:

Hengyang Lin - San Jose CA
Andrew J. Franklin - Santa Clara CA
Umer Ahmed Khan - Fremont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G11C 1700

US Classification:

365 94, 365196, 365203

Abstract:

A ROM system which provides for reduced size and power consumption. This ROM systems allows for inverting the programming and sensing of information in bit cells of the ROM to reduce the number of transistors in bit cells of the ROM. Further bit cells of the ROM provide that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed.

US Patent:

6642587, Nov 4, 2003

Filed:

Aug 7, 2002

Appl. No.:

10/214021

Inventors:

Hengyang Lin - San Jose CA
Andrew J. Franklin - Santa Clara CA
Ernes Ho - Sunnyvale CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01L 2976

US Classification:

257390, 257391, 438128, 438129, 438130, 438275, 438278, 438290

Abstract:

A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed. Further, where a bit cell does not provide a transistor between the bit line and the word line a bit cell region in the substrate can consist substantially of an isolating dielectric material.

US Patent:

6711051, Mar 23, 2004

Filed:

Sep 5, 2002

Appl. No.:

10/235530

Inventors:

Weipeng Zhang - San Francisco CA
Andrew J. Franklin - Santa Clara CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G11C 1100

US Classification:

365154, 365203, 36518902

Abstract:

A SRAM system which provides for reduced power consumption. The SRAM system utilizes an array of bit cells. Columns of bit cells in the array are partitioned into sections. Each section of bit cells shares a local bit line. A sector select circuit provides for precharging the local bit lines. The sector select circuit also includes a mux for connecting a local bit line to a global bit line. The sector select circuit includes a device for detecting when a sector select signal and a column select signal are present. When both of these signals are present the sector select circuit couples the local bit line with the global bit line, and disengages the precharging of the local bit line.

US Patent:

6992927, Jan 31, 2006

Filed:

Jul 8, 2004

Appl. No.:

10/895710

Inventors:

Yuri Mirgorodski - Sunnyvale CA, US
Andrew J. Franklin - Santa Clara CA, US
Hengyang (James) Lin - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G11C 16/04

US Classification:

36518505, 3651851, 36518514

Abstract:

An integrated nonvolatile memory circuit having a plurality of control devices. Separate devices execute distinct control, erase, write and read operations, thereby allowing each device to be individually selected and optimized for performing its respective operation.

US Patent:

7020027, Mar 28, 2006

Filed:

Jul 8, 2004

Appl. No.:

10/895712

Inventors:

Yuri Mirgorodski - Sunnyvale CA, US
Andrew J. Franklin - Santa Clara CA, US
Peter J. Hopper - San Jose CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G11C 16/04

US Classification:

36518528, 36518505, 36518514, 3651852

Abstract:

A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.

US Patent:

7042763, May 9, 2006

Filed:

Jul 8, 2004

Appl. No.:

10/895711

Inventors:

Yuri Mirgorodski - Sunnyvale CA, US
Peter J. Hopper - San Jose CA, US
Andrew J. Franklin - Santa Clara CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G11C 11/34

US Classification:

36518505, 3651851, 36518514

Abstract:

A method of selectively programming nonvolatile memory cells in which multiple programming voltages are used to obtain the desired voltage on the storage nodes of the cells selected for programming, while the storage nodes of unselected cells remain undisturbed.

US Patent:

7061792, Jun 13, 2006

Filed:

Aug 10, 2002

Appl. No.:

10/215678

Inventors:

Hengyang Lin - San Jose CA, US
Andrew J. Franklin - Santa Clara CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G11C 11/00
G11C 7/00
G11C 8/00

US Classification:

365154, 36518908, 365195, 365204, 365214, 36523003, 36523006

Abstract:

In a SRAM structure, power consumption is reduced by providing a structure which allows specific memory cells to be selected using word lines and column select lines, and reducing the load on the column address lines by dividing the load into sectors. The dividing into sectors is achieved by making use of sector select lines for selecting two or more rows of cells, and logically ANDing the sector select lines with the column select lines.

Author:

Andrew Franklin

ISBN #:

0750688521

Author:

Andrew Franklin

ISBN #:

0750688564

Author:

Andrew Franklin

ISBN #:

0750688904