Alfred P Chan

Author:

Alfred L. Chan

ISBN #:

0199244065

US Patent:

50105086, Apr 23, 1991

Filed:

Feb 14, 1989

Appl. No.:

7/311294

Inventors:

Hon P. Sit - Fremont CA
David Galbi - Mountain View CA
Alfred K. Chan - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 501
G06F 750

US Classification:

364748

Abstract:

In a floating-point subtraction of two numbers where a normalized result is needed, a prenormalization circuit predicts the number of leading zeroes which will appear in the resultant mantissa, due to the close value of the two source operands. The prenormalization circuit then causes appropriate left shifts of the two operand mantissas prior to the subtraction (two's complement addition) is performed, wherein the resultant mantissa will already be normalized.

US Patent:

49012703, Feb 13, 1990

Filed:

Sep 23, 1988

Appl. No.:

7/248797

Inventors:

David Galbi - Mountain View CA
Alfred K. Chan - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 750
G06F 752

US Classification:

364786

Abstract:

A four-to-two adder for adding four numbers and generating two numbers which has the same sum as the sum of the four input numbers is used to add partial products in a multiplier. A plurality of adder cells are arranged in parallel to process corresponding bits of the four numbers. Each adder cell couples three of the four input bits to the next stage. A four-bit parity circuit is used to control two multiplexers which select signals from a carry generator and the one input signal which is not coupled to the subsequent adder cell stage to provide two output bits corresponding to the two output numbers.

US Patent:

50273086, Jun 25, 1991

Filed:

Feb 14, 1989

Appl. No.:

7/311296

Inventors:

Hon P. Sit - Fremont CA
David Galbi - Mountain View CA
Alfred K. Chan - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 738
G06F 700

US Classification:

364748

Abstract:

In a floating-point addition (and/or subtraction) of two normalized numbers where a normalized result is also desired, a generation of a carry (overflow) or a borrow from the most significant bit of a minuend operation will cause the resultant mantissa not to be normalized. A dual adder scheme is used to always provide a normalized result. One adder provides an unshifted result while the second adder provides a shifted result. A logic circuit looks for a carry out when performing addition and a bit value of the msb when performing subtraction to select the output from the adder providing the proper normalization. Rounding logic circuitry is used to predict the rounding of the resultant mantissa and carry bits are coupled as a carry-in to the adders to achieve the proper rounding in the same clock cycle as the adding/subtracting of the two mantissas.

US Patent:

57322414, Mar 24, 1998

Filed:

Dec 20, 1993

Appl. No.:

8/170642

Inventors:

Alfred K. Chan - Milpitas CA

Assignee:

Mos Electronics, Corp. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

395458

Abstract:

A memory cache apparatus compatible with a wide variety of bus transfer types including non-burst and burst transfers. In burst mode, a "demand word first" wrapped around quad fetch order is supported. The cache memory system decouples the main memory subsystem from the host data bus so as to accommodate parallel cache-hit and system memory transfer operations for increased system speed and to hide system memory write-back cycles from the microprocessor. Differences in the speed of the local and system buses are accommodated, and an easy migration path from non-burst mode microprocessor based systems to burst mode microprocessor based systems is provided. Various memory organizations are accommodated including direct-mapped or one-way set associative, two-way set associative, and four-way set associative.

US Patent:

54887097, Jan 30, 1996

Filed:

Apr 1, 1991

Appl. No.:

7/678912

Inventors:

Alfred K. Chan - Milpitas CA

Assignee:

MOS Electronics, Corp. - Sunnyvale CA

International Classification:

G06F 1300
G06F 1328

US Classification:

395445

Abstract:

A memory cache apparatus compatible with a wide variety of bus transfer types including non-burst and burst transfers. The memory cache apparatus includes a random access memory, a host port, and a system port. The memory cache apparatus further includes an input register connected to the host port for selectively writing data to the random access memory and an output register connected to the system port for receiving data from the random access memory and selectively furnishing the data to the host port or the system port. In one embodiment, the input register is a memory write register, and the output register includes a read hold register and a write back register. A cache memory system decouples a main memory subsystem from a host data bus so as to accommodate parallel cache-hit and system memory transfer operations for increased system speed and to hide system memory write-back cycles from a microprocessor. Differences in the speed of the local and system buses are accommodated, and an easy migration path from non-burst mode microprocessor based systems to burst mode microprocessor based systems is provided. Various memory organizations are accommodated including direct-mapped or one-way set associative, two-way set associative, and four-way set associative.