Alexander Ivanivich Korobkov from 5532 Le Franc Dr, San Jose, CA 95118, Phone: 4084481638

Us Patents

Circuit Reduction Technique For Improving Clock Net Analysis Performance
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US Patent:

6895524, May 17, 2005
Filed:

Sep 28, 2001
Appl. No.:

09/967579
Inventors:

Alexander Korobkov - Sunnyvale CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F001/04
US Classification:

713500, 716 2, 716 4, 716 5, 716 6, 716 7, 716 8, 716 18, 703 14
Abstract:

A method for reducing a transistor circuit netlist for clock network timing verification is provided. Further, a simulation tool that reduces a transistor circuit netlist such that nonlinear circuit properties are preserved is provided. Further, a computer system that improves clock network performance by simulating a netlist that is generated from a reduced transistor circuit netlist is provided.

Method And Apparatus For Performing Operation On Physical Design Data
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US Patent:

6912705, Jun 28, 2005
Filed:

Jun 27, 2002
Appl. No.:

10/185502
Inventors:

Alexander I. Korobkov - Sunnyvale CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F009/455
G06F017/50
G06F009/45
US Classification:

716 11, 716 2, 716 3, 716 4, 716 5, 716 7, 716 8, 716 9, 716 10, 716 12
Abstract:

A method performs an operation on physical design data stored as data objects in a database. Each data object represents a design figure of an integrated circuit (IC) design laid-out on an IC design area. The method includes (a) dividing the IC design area into a second plurality of sub-areas, (b) assigning an area property to each of the data objects, the area property indicating the sub-areas on which at least part of the corresponding design figure is to be located, (c) selecting a first data object, and (d) conducting an operation involving the first data object and a second data object involving selecting the second data object from a subset of data objects having an area property indicating a sub-area indicated by an area property of the first data object, and performing the operation on the first data object and the second data object.

Method And Apparatus For Predicting Clock Skew For Incomplete Integrated Circuit Design
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US Patent:

7107200, Sep 12, 2006
Filed:

Oct 3, 2003
Appl. No.:

10/678535
Inventors:

Alexander I. Korobkov - Sunnyvale CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 17/50
US Classification:

703 13, 716 6
Abstract:

Prediction of a clock skew for an incomplete integrated circuit design, includes (a) selecting a first metal layer having at least one clock design figure, (b) placing, for a minimum clock skew prediction, clock source locations on the clock design figure in accordance with a first predetermined minimum distance between adjacent clock source locations, (c) placing, for a maximum clock skew prediction, a clock source location on a largest clock design figure in the first layer, such that the clock source location has a largest distance from a via to a lower layer, and (d) placing, for an intermediate clock skew prediction, clock source locations on intersections between the clock design figure and a virtual clock grid created for the first metal layer, the virtual clock grid having a predetermined offset from a design boundary and a predetermined pitch between grid lines.

Graph Pruning Scheme For Sensitivity Analysis With Partitions
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US Patent:

7421671, Sep 2, 2008
Filed:

Aug 31, 2006
Appl. No.:

11/469460
Inventors:

Alexander Korobkov - Sunnyvale CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 17/50
US Classification:

716 5, 716 7, 703 16
Abstract:

A method of analyzing a circuit simulation comprising pruning a signal flow graph. Pruning the signal flow graph includes selecting a current vertex from a multiple input vertices in the signal flow graph. Each one of the input vertices is connected to a primary input of the signal flow graph. Determining if the current vertex includes at least one of a sensitivity parameter or a sensitivity variable. If the current vertex includes at least one of a sensitivity parameter or a sensitivity variable then the current vertex is identified as being part of a sensitivity path and is added to a first sub-group of vertices. Pruning the signal flow graph also includes determining if any remaining non-visited neighbor vertices remain to be analyzed. If any remaining non-visited neighbor vertices remain to be analyzed then selecting a neighboring vertex and determining if the selected neighbor vertex is identified as a sensitivity path. If the selected neighbor vertex is identified as a sensitivity path, then the first sub-group of vertices are output into a final pruned signal flow graph.

Method To Improve Time Domain Sensitivity Analysis Performance
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US Patent:

7484195, Jan 27, 2009
Filed:

Aug 30, 2006
Appl. No.:

11/468431
Inventors:

Alexander Korobkov - Sunnyvale CA, US
Assignee:

Sun Microsystems, Inc. - Santa Clara CA
International Classification:

G06F 17/50
G06F 17/16
US Classification:

716 6, 703 2, 703 16
Abstract:

A method for performing sensitivity analysis on a circuit design is provided. The method initiates with identifying a partition of the circuit design. The method includes determining whether the partition belongs to a sensitivity graph, where the sensitivity graph represents a relationship between variables and parameters of the partition. If the partition belongs to the sensitivity graph, then the method includes, applying linear matrix factors to provide a solution to a system of linear equations and multiplying the solution by a vector to derive sensitivities for the circuit design.

Performance Of Circuit Simulation With Multiple Combinations Of Input Stimuli
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US Patent:

7865348, Jan 4, 2011
Filed:

Jan 31, 2007
Appl. No.:

11/669458
Inventors:

Wai Chung W. Au - San Jose CA, US
Alexander I. Korobkov - San Jose CA, US
Assignee:

Oracle America, Inc. - Redwood City CA
International Classification:

G06F 17/50
US Classification:

703 15, 703 13, 703 14, 716 4
Abstract:

This invention provides techniques and tools for reducing circuit simulation time when an electronic circuit with multiple input vectors is simulated. Instead of running the simulation for each input vector one at a time, the circuit-simulation application runs the simulation of the circuit for all input vectors simultaneously. Efficiencies in the simulation are obtained during each iteration of a transient analysis by grouping circuit instances with different input vectors based on a predetermined criteria, and producing a combined solution for circuit instances within each group.

Fast Reduction Of System Models
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US Patent:

7949970, May 24, 2011
Filed:

Oct 17, 2007
Appl. No.:

11/874053
Inventors:

Alexander Korobkov - San Jose CA, US
Wai Chung W. Au - San Jose CA, US
Assignee:

Oracle America, Inc. - Redwood City CA
International Classification:

G06F 9/45
US Classification:

716103
Abstract:

Techniques are provided for fast reduction of a system model, such as fast parasitics reduction of an electrical design. Delta loops, which comprise three nodes connected by three edges, may be identified. The netlist can be annotated with the number of delta loops to which an edge belongs and a delta loop identifier. Delta loops that share an edge may be assigned the same identifier. Identifying delta loops may be based on the intersection of binary search trees that are based on the netlist. In one embodiment, a cost of removing a node from the netlist is determined. Based on the annotations to the edges connected to a node under consideration for removal, the total number of delta loops that are shared by pairs of edges is determined. Based, at least in part, on the total number of common delta loops, a cost is determined of removing the node.

System, Method And Apparatus For Sensitivity Based Fast Power Grid Simulation With Variable Time Step
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US Patent:

7953581, May 31, 2011
Filed:

Jun 19, 2008
Appl. No.:

12/142273
Inventors:

Michael Yu - Santa Clara CA, US
Alexander I. Korobkov - Santa Clara CA, US
Assignee:

Oracle America, Inc. - Redwood City CA
International Classification:

G06F 17/50
US Classification:

703 2, 703 6, 703 14
Abstract:

A system and method of analyzing a power grid in an integrated circuit includes inputting a circuit design to a test bench, inputting a plurality of initial values for the circuit design in to the test bench, setting a current time t to 0 value for an initial time (t) of the operation of the circuit design, representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model, describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations, storing the plurality of linear equations in a matrix Yfor time t, resolving the matrix Yto determine a DC operating point, updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t=t+h where h is a time step value equal to the current time t and a next simulated operation time, storing the updated plurality of linear equations in a matrix Yfor time t, inverting the matrix Yto form inverted matrix Y, resolving the inverted matrix Y, calculating a new time step and setting the current time t to t+h, comparing the new time step h to a plurality of time steps in a time step database, selecting one of the plurality of time steps substantially equal to the new time step and recalling a solution corresponding to the selected time step.