Alex E Henderson

US Patent:

6362993, Mar 26, 2002

Filed:

Nov 13, 2000

Appl. No.:

09/711989

Inventors:

Alex E. Henderson - Hillsborough CA
Walter E. Croft - San Mateo CA

Assignee:

Fast-Chip Incorporated - Sunnyvale CA

International Classification:

G11C 1500

US Classification:

365 49, 36518907

Abstract:

A content addressable memory device is provided which may include a novel CAM cell structure which reduces the total power dissipated by the CAM and improves the match time for the CAM. The novel CAM cell structure may include a CMOS implemented compare cell and a wide AND gate which combines the match decisions for each CAM cell into a match decision. The CAM cell structure may be implemented in a variety of different CAM devices, including dual port CAM devices, CAM devices with individual bit masking, event co-processors and database co-processors.

US Patent:

6378042, Apr 23, 2002

Filed:

Aug 10, 2000

Appl. No.:

09/636305

Inventors:

Alex E. Henderson - Hillsborough CA
Walter E. Croft - San Mateo CA

Assignee:

Fast-Chip, Inc. - Sunnyvale CA

International Classification:

G06F 1212

US Classification:

711128, 711137, 711122, 711134, 711159

Abstract:

A system and method for operating an associative memory cache device in a computer system. The system comprises a search client configured to search for data in a caching associative memory such as a content addressable memory (CAM); a caching associative memory element coupled to the search client for generating a matching signal; and a associative memory element coupled to the caching associative element configured to search for data not stored in the caching associative memory element. The search client issues a search request for data to associative cache element. If the matching data is found there, then such matching data is returned to the search client. Alternatively, if the data is not found, then the search request is issued to the main associative memory. The least frequently used data or the least recently used data in the associative memory cache are replaced with the matching data and the higher priority data.

US Patent:

6426647, Jul 30, 2002

Filed:

Sep 15, 2000

Appl. No.:

09/663865

Inventors:

Alex E. Henderson - Hillsborough CA

Assignee:

Fast-Chip, Inc. - Sunnyvale CA

International Classification:

G06F 738

US Classification:

326 39, 327404

Abstract:

A logic circuit comprises a dual rail drive circuit having a first rail and a second rail. The logic circuit further comprises a logic block having a first input coupled to receive an input signal from the first rail of the dual rail driver, and a second input coupled to receive an input signal from the second rail of the dual rail driver. In one embodiment, the input signal from the first rail of the dual rail driver can swing to a voltage level sufficient to turn on a p-channel transistor, and the input signal from the second rail of the dual rail driver can swing to a voltage level sufficient to turn on an n-channel transistor. For example, for a 0. 18 micron process the input signal from the first rail may have a voltage swing from VDD to VDD-400 MV, and the input signal from the second rail may a voltage swing from GROUND to 400 MV.

US Patent:

6446188, Sep 3, 2002

Filed:

Sep 1, 2000

Appl. No.:

09/654189

Inventors:

Alex E. Henderson - Hillsborough CA
Walter E. Croft - San Mateo CA

Assignee:

Fast-Chip, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

711206, 711119

Abstract:

A system for mapping a sparsely populated virtual space of variable sized memory objects to a more densely populated physical address space of fixed size memory elements for use by a host processor comprises an object cache for caching frequently accessed memory elements and an object manager for managing the memory objects used by the host processor. The object manager may further comprise an address translation table for translating virtual space addresses for memory objects received from the host processor to physical space addresses for memory elements, and a management table for storing data associated with the memory objects used by the host processor.

US Patent:

6470436, Oct 22, 2002

Filed:

Dec 1, 1998

Appl. No.:

09/203995

Inventors:

Walter E. Croft - San Mateo CA
Alex Henderson - Hillsborough CA

Assignee:

Fast-Chip, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

711206, 711209

Abstract:

A hardware or software apparatus, or a combination of both, is used for efficiently managing the dynamic allocation, access and release of memory used in a computational environment. This apparatus reduces, or preferably eliminates, the requirements for application housekeeping, such as garbage collection, by providing substantially more deterministic dynamic memory management operations. Housekeeping, or garbage collection, such as memory compaction and unused space retrieval, are reduced or eliminated. When housekeeping is eliminated, all dynamic memory invocations become substantially deterministic. The invention maps all or a part of a large, sparsely populated logical memory address space used to store dynamically allocated objects, to a smaller, denser physical memory address space. This invention results in a reduction in processing overhead in the computational environment, such as an operating system, which enhances performance, since the application no longer requires housekeeping functions from the environment. This process is particularly applicable to software components developed utilizing object oriented programming, which is more likely to use temporary memory allocation and release, thereby requiring significant housekeeping functions in the prior art.

US Patent:

6674308, Jan 6, 2004

Filed:

Nov 9, 2001

Appl. No.:

10/014821

Inventors:

Alex E. Henderson - Hillsborough CA
Walter E. Croft - San Mateo CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 19094

US Classification:

326114, 326104, 326125

Abstract:

A low power wired OR circuit of the present invention comprises a plurality of logic blocks for pulling a wired OR signal line low in response to certain conditions, a differential pair of lines, such as the wired OR signal line and a reference signal line, and a sensing device coupled to the reference signal line and the wired OR signal line to receive the wired OR signal and the reference signal respectively and to detect a difference between the two signals. Having a differential pair of lines is advantageous because it maintains noise immunity for small voltage swings on the wired OR signal line, thereby reducing power dissipation in the wired OR circuit. A common current source coupled to each logic block through a common return path allows the low power wired OR circuit to control a discharge rate at which the wired OR line discharges.

US Patent:

6721842, Apr 13, 2004

Filed:

Nov 7, 2001

Appl. No.:

10/005986

Inventors:

Alex E. Henderson - Hillsborough CA
Walter E. Croft - San Mateo CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711101, 711105, 711108

Abstract:

A boundary addressable memory (BAM) array comprises a plurality of BAM word modules, each BAM word module comprises a plurality of BAM cells for performing arithmetic comparisons between input data and an upper bound value and a lower bound value stored in each BAM cell to generate a matching signal indicating whether the input data is not greater than the upper bound value and not less than the lower bound value or whether the input data is not greater than the lower bound value and not less than the upper bound value.

US Patent:

6748484, Jun 8, 2004

Filed:

Aug 10, 2000

Appl. No.:

09/637131

Inventors:

Alex E. Henderson - Hillsborough CA
Walter E. Croft - San Mateo CA
Raymond M. Chu - Saratoga CA
Vishal Sarin - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711108, 711128, 711156, 365 49

Abstract:

A system and method for determining a best match from a plurality of matches received in response to a search input for an associative memory includes a priority field associated with each data item stored in the associative memory. The priority field corresponds to criteria that is used to order the priority of the data items in the associative memory. A match resolution circuit is coupled to receive match signals from an associative memory, such as a CAM, and the priority fields of the matching data items. The match resolution structure compares the priority fields of the matching data items to determine which data item has the highest priority. The match resolution structure indicates the data item with the highest priority in the priority field as the best match of the associative memory for the particular search input.