Alan D Hales

US Patent:

7039823, May 2, 2006

Filed:

Apr 24, 2003

Appl. No.:

10/422275

Inventors:

Alan D. Hales - Richardson TX, US
Anthony M. Hill - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1/12

US Classification:

713400, 713401, 713500

Abstract:

An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.

US Patent:

7183570, Feb 27, 2007

Filed:

Apr 11, 2005

Appl. No.:

11/103781

Inventors:

Lee D. Whetsel - Parker TX, US
Alan Hales - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/58

US Classification:

257 48, 324765

Abstract:

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. The response patterns include one of expected data and mask data input on an output pad of the die/IC and the other of expected data and mask data input on another pad of the die/IC, which may be an input pad or an output pad. In addition to functional testing, scan testing of die and ICs is also possible.

US Patent:

7389455, Jun 17, 2008

Filed:

May 14, 2006

Appl. No.:

11/383211

Inventors:

Alan Hales - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/28

US Classification:

714726, 714 30, 714 31, 714 36, 714709, 714724, 714727, 714729, 714731, 714733, 714734, 712227

Abstract:

A system and method for initializing a register file during a test period for an integrated circuit, wherein the register file has one or more input ports. A counter, when enabled, is initialized and counts at each write cycle of the register file and outputs a current count value to the input ports of the register file to pre-load the register file to a known state.

US Patent:

7469372, Dec 23, 2008

Filed:

May 4, 2006

Appl. No.:

11/381624

Inventors:

Lewis Nardini - Richardson TX, US
Alan D. Hales - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/28

US Classification:

714726

Abstract:

A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This technique supplies a predefined pattern to parallel scan chains following power-on reset. The predefined pattern places the device or module in a architecturally specified reset state. The parallel scan chains are required for structural manufacturing test. Once the power-on reset scanning is complete, the power-on reset sequencer indicates completion of state initialization to other circuits.

US Patent:

7491970, Feb 17, 2009

Filed:

Jan 9, 2008

Appl. No.:

11/971561

Inventors:

Lee D. Whetsel - Parker TX, US
Alan Hales - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/58
G01R 31/26

US Classification:

257 48, 438 18, 324765

Abstract:

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i. e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

US Patent:

7655946, Feb 2, 2010

Filed:

Dec 8, 2008

Appl. No.:

12/329957

Inventors:

Lee D. Whetsel - Parker TX, US
Alan Hales - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/58

US Classification:

257 48, 257E21524, 324765

Abstract:

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i. e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

US Patent:

7842949, Nov 30, 2010

Filed:

Dec 15, 2009

Appl. No.:

12/638441

Inventors:

Lee D. Whetsel - Parker TX, US
Alan Hales - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/58

US Classification:

257 48, 257E21524

Abstract:

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i. e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

US Patent:

8205125, Jun 19, 2012

Filed:

Oct 23, 2009

Appl. No.:

12/604397

Inventors:

Alan David Hales - Richardson TX, US
Srujan Kumar Nakidi - Adilabad, IN
Rubin Ajit Parekhji - Bangalore, IN
Srivaths Ravi - Bangalore, IN
Rajesh Kumar Tiwari - Lucknow, IN

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01R 31/3177
G01R 31/40

US Classification:

714729, 714727

Abstract:

A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can selectively control scan-in, scan-out and capture phases of scan tests for different scan chains of the IC to be independent. The number of pins required to interface the test controller with an external tester is less than the number of partitions that the test controller can support. According to another aspect, an IC includes a register corresponding to each partition to support transition fault (or LOS) testing. According to another aspect, an IC with partitioned scan chains includes serial to parallel and parallel to serial converters, thereby minimizing the external pins required to support scan tests.

Address:

3082 Greenfield Dr, Richardson, TX 75082

Phone:

9726990541

VIN:

5FNRL38767B058160

Make:

HONDA

Model:

ODYSSEY

Year:

2007